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MPC8535ECVTATH Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc |
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MPC8535ECVTATH Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 126 page  Pin Map MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15 UART_SOUT[0:1] Transmit data AF10,AA12 O OVDD 5,9,22, 10,29 I2C interface IIC1_SCL Serial clock AG21 I/O OVDD 4,21,29 IIC1_SDA Serial data AH22 I/O OVDD 4,21,29 IIC2_SCL Serial clock AH15 I/O OVDD 4,21,29 IIC2_SDA Serial data AG14 I/O OVDD 4,21,29 SerDes1(x4) SD1_TX[7:4] Transmit Data (+) Y23,W21,V23,U21 O XVDD — SD1_TX[7:4] Transmit Data(-) Y22,W20,V22,U20 O XVDD — SD1_RX[7:4] Receive Data(+) AC28,AB26,AA28,Y26 I XVDD — SD1_RX[7:4] Receive Data(–) AC27,AB25,AA27,Y25 I XVDD — Reserved — R21,P23,N21,M23, R20,P22,N20,M22 —— 18 Reserved — T26,R28,P26,N28, T25,R27,P25,N27 —— 33 SD1_PLL_TPD PLL test point Digital V28 O XVDD 18 SD1_REF_CLK PLL Reference clock U28 I XVDD — SD1_REF_CLK PLL Reference clock complement U27 I XVDD — Reserved — T22 — — 18 Reserved — T23 — — 18 SerDes2(x1) SD2_TX[0] Transmit data(+) P11 O X2VDD — SD2_TX[0] Transmit data(-) P12 O X2VDD — SD2_RX[0] Receive data(+) P6 I X2VDD — SD2_RX[0] Receive data(-) P7 I X2VDD — Reserved — M11,M12 — — 18 Reserved — N8, N9 — — 34 SD2_PLL_TPD PLL test point Digital L7 O X2VDD 18 SD2_REF_CLK PLL Reference clock M6 I X2VDD — SD2_REF_CLK PLL Reference clock complement M7 I X2VDD — Reserved — L8 — X2VDD 18 Reserved — L9 — X2VDD 18 Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
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