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MPC8535ECVTATH Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc |
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MPC8535ECVTATH Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 126 page  MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Pin Map Freescale Semiconductor 14 TSEC3_TX_CLK Transmit clock In U10 I LVDD — TSEC3_GTX_CLK Transmit clock Out U5 O LVDD — TSEC3_CRS Carrier sense T10 I/O LVDD 17 TSEC3_COL Collision detect T9 I LVDD — TSEC3_RXD[7:0] Receive data U12,U13,U6,V6,V1,U3, U2,V3 ILVDD — TSEC3_RX_DV Receive data valid V2 I LVDD — TSEC3_RX_ER Receive data error T4 I LVDD — TSEC3_RX_CLK Receive clock U1 I LVDD — IEEE 1588 TSEC_1588_CLK Clock In W9 I LVDD 29 TSEC_1588_TRIG_IN[0:1] Trigger In W8,W7 I LVDD 29 TSEC_1588_TRIG_OUT[0:1] Trigger Out U11,W10 O LVDD 5,9,29 TSEC_1588_CLK_OUT Clock Out V10 O LVDD 5,9,29 TSEC_1588_PULSE_OUT1 Pulse Out1 V11 O LVDD 5,9,29 TSEC_1588_PULSE_OUT2 Pulse Out2 T11 O LVDD 5,9,29 eSDHC SDHC_CMD Command line AH10 I/O OVDD 29 SDHC_CD/GPIO[4] Card detection AH11 I OVDD — SDHC_DAT[0:3] Data line AG12,AH12,AH13, AG11 I/O OVDD 29 SDHC_DAT[4:7] / SPI_CS[0:3] 8-bit MMC Data line / SPI chip select AE8,AC10,AF9,AA10 I/O OVDD 29 SDHC_CLK SD/MMC/SDIO clock AG13 I/O OVDD 29 SDHC_WP/GPIO[5] Card write protection AG10 I OVDD 1, 32 eSPI SPI_MOSI Master Out Slave In AF8 I/O OVDD 29 SPI_MISO Master In Slave Out AD9 I OVDD 29 SPI_CLK eSPI clock AD8 I/O OVDD 29 SPI_CS[0:3] / SDHC_DAT[4:7] eSPI chip select / SDHC 8-bit MMC data AE8,AC10,AF9,AA10 I/O OVDD 29 DUART UART_CTS[0:1] Clear to send AE11,Y12 I OVDD 29 UART_RTS[0:1] Ready to send AB12,AD12 O OVDD 29 UART_SIN[0:1] Receive data AC12,AF12 I OVDD 29 Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
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