MPC8535ECVTATH datasheet(71/126 Pages) FREESCALE

No. de pieza	MPC8535ECVTATH

Descripción Electrónicos	PowerQUICC??III Integrated Processor Hardware Specifications

PDF	126 Pages

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Fabricante Electrónico	FREESCALE [Freescale Semiconductor, Inc]

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enhanced Local Bus Controller (eLBC)

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Figure 40. Local Bus Signals (PLL Bypass Mode)

Table 54 describes the general timing parameters of the local bus interface at VDD = 3.3 V DC with PLL disabled.

Table 54. Local Bus General Timing Parameters—PLL Bypassed

Parameter

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

—

Input setup to local bus clock (except LUPWAIT)

tLBIVKH1

5.1

—

4, 5

LUPWAIT input setup to local bus clock

tLBIVKL2

4.2

—

4, 5

Input hold from local bus clock (except LUPWAIT)

tLBIXKH1

-1.4

—

4, 5

LUPWAIT input hold from local bus clock

tLBIXKL2

-2.0

—

4, 5

LALE output transition to LAD/LDP output transition (LATCH hold time)

tLBOTOT

1.4

—

Local bus clock to output valid (except LAD/LDP and LALE)

tLBKLOV1

—0.5

Output Signals:

LA[27:31]/LBCTL/LOE

tLBKLOV2

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal:

LAD[0:31]

tLBIVKH1

tLBKLOX1

tLBKLOZ2

tLBOTOT

tLBKLOX2

tLBKLOV1

tLBKLOV3

tLBKLOZ1

tLBKLOV4

tLBIXKL2

tLBIVKL2

UPM Mode Input Signal:

LUPWAIT

MPC8535ECVTATH Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc

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