MPC8535ECVTATH datasheet(91/126 Pages) FREESCALE

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High-Speed Serial Interfaces

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the two complimentary input

voltages: VSDn_RX - VSDn_RX. The VID value can be either positive or negative.

Differential Peak Voltage, VDIFFp

The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak

Voltage, VDIFFp = |A - B| Volts.

Differential Peak-to-Peak, VDIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to

-(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential

receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp =

2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential

peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p

= 2*|VOD|.

Common Mode Voltage, Vcm

The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange

circuit and ground. In this example, for SerDes output, Vcm_out = VSDn_TX + VSDn_TX = (A + B)

/ 2, which is the arithmetic mean of the two complimentary output voltages within a differential

pair. In a system, the common mode voltage may often differ from one component’s output to the

other’s input. Sometimes, it may be even different between the receiver input and driver output

circuits within the same component. It is also referred as the DC offset in some occasion.

Figure 57. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common

mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values,

the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each

signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential

swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500

mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage

(VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.20.2

SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding

SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference

clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.

Differential Swing, VID or VOD = A – B

A Volts

B Volts

n_TX or

n_RX

n_TX or

n_RX

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)

Vcm = (A + B) / 2

MPC8535ECVTATH Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

MPC8535ECVTATH Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

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