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MPC8535ECVTATH Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc |
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MPC8535ECVTATH Datasheet(HTML) 94 Page - Freescale Semiconductor, Inc |
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94 / 126 page ![]() MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 High-Speed Serial Interfaces Freescale Semiconductor 94 Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled) Figure 61. Single-Ended Reference Clock Input DC Requirements 2.20.2.3 Interfacing With Other Differential Signaling Levels With on-chip termination to SnGND (xcorevss), the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL (Low Voltage Positive Emitter-Coupled Logic) outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 62 to Figure 65 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8535E SerDes reference clock receiver requirement provided in this document. SD n_REF_CLK SD n_REF_CLK Vcm 200mV < Input Amplitude or Differential Peak < 800 mV Vmax < Vcm + 400 mV Vmin > Vcm – 400 mV SD n_REF_CLK SD n_REF_CLK 400 mV < SD n_REF_CLK Input Amplitude < 800 mV 0V |
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