AS3525 datasheet(74/194 Pages) AMSCO

74 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

Table 56 NAF configuration register

Name

Base

Default

NAFConfig

AS3525_NAND_FLASH_BASE

0x00

NAF Configuration Register

Offset 0x0000

The register is used for basic setup. 8 or 16-bit data width, little or big endian can

be selected. DMA and FIFO on/off can be controlled as well as duty cycle and

duration of read & write signals.

Bit

Bit Name

Default

Access

Bit Description

19:16

write_strobe_low [3:0]

0x00

R/W

low time (# of PCLK cycles + 1) of the output ‘naf_we_n’

(e.g. a value of 1 will keep naf_we_n at ‘0’ for 3 PCLK

cycles during write)

15:12

write_strobe_high [3:0]

0x00

R/W

high time (# of PCLK cycles + 2) of the output ‘naf_we_n’

(e.g. a value of 0 will keep naf_we_n at ‘1’ for 2 PCLK

cycles during write)

11:8

read_strobe_low [3:0]

0x00

R/W

low time (# of PCLK cycles + 1) of the output ‘naf_re_n’

(e.g. a value of 2 will keep naf_re_n at ‘0’ for 3 PCLK cycles

during read)

7:4

read_strobe_high [3:0]

0x00

R/W

high time (# of PCLK cycles + 2) of the output ‘naf_re_n’

(e.g. a value of 0 will keep naf_re_n at ‘1’ for 2 PCLK cycles

during read)

dma_on

0x0

R/W

0: DMA is disabled and all DMA request signals are tied to

1: DMA is enabled

fifo_staticreset_n

0x0

R/W

0: FIFO is reset

1: FIFO is enabled

big_endian

0x0

R/W

0: little endian (FIFO data word will be processed in the

order word(7:0), word(15:8), word(23:16) and word(31:24)

when x16_device is 0; word(15:0) and word(31:16) when

x16_device is 1

1: big endian (FIFO data word will be processed in the order

word(31:24), word(23:16), word(15:8) and word(7:0) when

x16_device is 0; word(31:16) and word(15:0) when

x16_device is 1

Note: big_endian is only supported for r/w access through

x16_device

0x0

R/W

0: X8 Device (for NAND flash with 8-bit data bus)

1: X16 Device (for NAND flash with 16-bit data bus)

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