AS3525 datasheet(45/194 Pages) AMSCO

45 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

Watchdog control register, WdogControl

This is a read/write register that enables the software to control the watchdog unit.

Table 23 watchdog control register

Name

Base

Default

WdogControl

AS3525_WDT_BASE

0x04

Watchdog Control Register

Offset: 0x08

Bit

Bit Name

Default

Access

Bit Description

RESEN

R/W

Enable Watchdog reset output (WDOGRES). Acts as a mask

for the reset output.

0: disable the reset

1: enable the reset

INTEN

R/W

Enable the interrupt event (WDOGINT).

0: disable the counter and interrupt

1: enable the counter and interrupt

Watchdog clear interrupt register, WdogIntClr

A write of any value to this location clears the watchdog interrupt, and reloads the counter from the value in WdogLoad.

Raw interrupt status register, WdogRIS

This register indicates the raw interrupt status from the counter. This value is ANDed with the inerrupt enable bit from the control register to create

the masked interrupt, which is passed to the interrupt output pin.

Table 24 watchdog raw interrupt status register

Name

Base

Default

WdogRIS

AS3525_WDT_BASE

Watchdog interrupt status register

Offset: 0x10

Bit

Bit Name

Default

Access

Bit Description

Watchdog Interrupt

Enabled interrupt status from the counter

Interrupt status register, WdogMIS

This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the INTEN bit from

the control register, and is the same value which is passed to the interrupt output pin.

Name

Base

Default

WdogMIS

AS3525_WDT_BASE

Watchdog raw interrupt status register

Offset: 0x14

Bit

Bit Name

Default

Access

Bit Description

Raw Watchdog

Interrupt

Raw interrupt status from the counter

Table 25 watchdog interrupt status register

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