AS3525 datasheet(77/194 Pages) AMSCO

77 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

Table 59 NAF data register

Name

Base

Default

NAFData

AS3525_NAND_FLASH_BASE

0x0000

Data Register

Offset 0x000C

The NAFData register offers unbuffered access to the data bus of the NAND flash

device.

Bit

Bit Name

Default

Access

Bit Description

15:0

NAFData

0x01

R/W

For X8 devices (8-bit data bus) only bits 7:0 are relevant, other

bits are ignored

For X16 devices (16-bit data bus) all are relevant

Table 60 NAF mode register

Name

Base

Default

NAFMode

AS3525_NAND_FLASH_BASE

0x00

Mode register

Offset 0x0010

The NAFMode register controls NAND flash read/write/erase procedures.

Bit

Bit Name

Default

Access

Bit Description

write protection

0x0

R/W

0: write protection is on

1: write protection is off (when ‘power_on’ is 1)

6:5

ecc [1:0]

0x0

R/W

0: error code correction disabled

1: error code correction enabled (when ‘ce’ is 1)

2: stop error code correction, disable read/write strobes and

disable ‘naf_do’ (when ‘ce’ is 1). Use this mode when reading

the NAFEcc register

3: Reset NAFEcc register contents, ‘ecc’ changes to value 1

(enable mode) automatically after the next PCLK cycle

0x0

R/W

controls ‘chip enable’

0: output ‘naf_ce_n’ is set to ‘1’ (device is disabled)

1: output ‘naf_ce_n’ is set to ‘0’ (device is enabled)

0x0

always ‘0’

power_on

0x0

R/W

0: power off (all output enable signals are turned off)

1: power on

ale

0x0

R/W

controls ‘address latch enable’

0: output ‘naf_ale’ is set to ‘0’

1: output ‘naf_ale’ is set to ‘1’ (Address Latch Cycle)

cle

0x0

R/W

controls ‘command latch enable’

0: output ‘naf_cle’ is set to ‘0’

1: output ‘naf_cle’ is set to ‘1’ (Command Latch Cycle)

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