UPD17708 datasheet(26/356 Pages) NEC

26 / 356 page

µPD17704, 17705, 17707, 17708, 17709

2.3 Program Counter

2.3.1 Configuration of program counter

Figure 2-3 shows the configuration of the program counter.

As shown in this figure, the program counter consists of a 13-bit binary counter and a 1-bit segment register

(SGR). Bits 11 and 12 of the program counter indicate a page.

The program counter specifies an address of the program memory.

Figure 2-3. Configuration of Program Counter

2.3.2 Segment register (SGR)

The segment register specifies a segment of the program memory.

Table 2-1 shows the relationships between the segment register and program memory.

The segment register is set only when the SYSCAL entry instruction is executed.

Table 2-1. Relationships between Segment Register and Program Memory

Value of Segment Register

Segment of Program Memory

Segment 0

Segment 1

2.4 Flow of Program

The flow of the program is controlled by the program counter that specifies an address of the program

memory.

The program flow when each instruction is executed is described below.

Figure 2-5 shows the value that is set to the program counter when each instruction is executed.

Table 2-2 shows the vector address when an interrupt is accepted.

2.4.1 Branch instruction

(1) Direct branch (“BR addr”)

The branch destination address of the direct branch instruction is in the same segment of the program

memory. In other words, a branch cannot be executed exceeding a segment.

(2) Indirect branch (“BR @AR”)

The branch destination addresses of the indirect branch instruction are all the addresses of the program

memory, i.e., addresses 0000H through 1FFFH for the

µPD17704, addresses 0000H through 2FFFH for

the

µPD17705, 17707, and 0000H through 3FFFH for the µPD17708 and 17709.

For further information, also refer to 5.3 Address Register (AR).

PC0

SGR

Page

PC12

PC11

PC10

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

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