UPD17708 datasheet(9/356 Pages) NEC

9 / 356 page

µPD17704, 17705, 17707, 17708, 17709

13.2

Basic Timer 0 ........................................................................................................................ 150

13.3

Timer 0 .................................................................................................................................. 163

13.4

Timer 1 .................................................................................................................................. 172

13.5

Timer 2 .................................................................................................................................. 179

13.6

Timer 3 .................................................................................................................................. 186

14. A/D CONVERTER ............................................................................................................................ 193

14.1

Outline of A/D Converter ..................................................................................................... 193

14.2

Input Selection Block ........................................................................................................... 194

14.3

Compare Voltage Generation and Compare Blocks ........................................................ 196

14.4

Comparison Timing Chart ................................................................................................... 199

14.5

Using A/D Converter ............................................................................................................ 200

14.6

Cautions on Using A/D Converter ...................................................................................... 201

14.7

Status at Reset ..................................................................................................................... 201

15. D/A CONVERTER (PWM mode) ...................................................................................................... 202

15.1

Outline of D/A Converter ..................................................................................................... 202

15.2

PWM Clock Selection Register ........................................................................................... 203

15.3

PWM Output Selection Block .............................................................................................. 204

15.4

Duty Setting Block ............................................................................................................... 207

15.5

Clock Generation Block ....................................................................................................... 211

15.6

D/A Converter Output Wave ................................................................................................ 211

15.7

Example of Using D/A Converter ........................................................................................ 214

15.8

Status at Reset ..................................................................................................................... 215

16. SERIAL INTERFACES ..................................................................................................................... 216

16.1

Outline of Serial Interfaces .................................................................................................. 216

16.2

Serial Interface 0 .................................................................................................................. 217

16.3

Serial Interface 1 .................................................................................................................. 245

17. PLL FREQUENCY SYNTHESIZER .................................................................................................. 255

17.1

Outline of PLL Frequency Synthesizer .............................................................................. 255

17.2

Input Selection Block and Programmable Divider ........................................................... 256

17.3

Reference Frequency Generator ......................................................................................... 260

17.4

Phase Comparator (

φ-DET), Charge Pump, and Unlock FF ............................................. 262

17.5

PLL Disabled Status ............................................................................................................ 266

17.6

Using PLL Frequency Synthesizer ..................................................................................... 267

17.7

Status at Reset ..................................................................................................................... 271

18. FREQUENCY COUNTER ................................................................................................................. 272

18.1

Outline of Frequency Counter ............................................................................................. 272

18.2

Input/Output Selection Block and Gate Time Control Block ........................................... 273

18.3

Start/Stop Control Block and IF Counter .......................................................................... 276

18.4

Using IF Counter .................................................................................................................. 283

18.5

Using External Gate Counter .............................................................................................. 285

18.6

Status at Reset ..................................................................................................................... 286

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