UPD17708 datasheet(71/356 Pages) NEC

71 / 356 page

µPD17704, 17705, 17707, 17708, 17709

Table 8-1. Peripheral Hardware Control Functions of Control Registers (2/8)

Peripheral

Control Register

Peripheral Hardware Control Function

At Reset

Clock

Hardware

Name

Address

Read/

Function

Set value

Power- WDT

Stop

Write

Symbol

& SP

reset

CE reset timer

06H

R/W

CECNT3

Sets number of CE reset timer

Retained Retained

carry counter

CECNT2

carry counts

CECNT1

CECNT0

MOVT bit

07H

R/W

Fixed to “0”

Retained

selection

MOVTSEL1 Sets bit transferred by MOVT (transferred

MOVTSEL0 to DBF1, 0 during 8-bit transfer)

Serial

Serial I/O0 wait

0AH

Fixed to “0”

0000

interface status judgment

SIO0WSTT Judges wait status of serial

During wait

During serial

interface 0

communication

Serial I/O0

0BH

R/W

Fixed to “0”

0000

clock selection

SBMD

Selects operation mode of I2C

Continues

Reception mode is

bus during slave transmission

processing

set automatically

SIO0CK1

Sets internal clck of serial

SIO0CK0

interface 0

Serial I/O0

0CH

R/W

Fixed to “0”

0000

interrupt mode

selection

SIO0IMD1

Sets interrupt condition of

SIO0IMD0

serial interface 0

Serial I/O0

0DH

SIO0SF8

Detects clock counter

Set at 8th clock

0000

status detection

SIO0SF9

Set at 9th clock

SBSTT

Detects number of clocks

Set from start condition to

(I2C bus mode)

9th clock

SBBSY

Detects start condition

Set from start condition to

(I2C bus mode)

stop condition

Serial I/O0 wait

0EH

R/W

SBACK

Sets and detects acknowledge Sets and detects 0, 1

0000

control

(I2C bus mode)

SIO0NWT

Enables wait

Enabled

Cleared

SIO0WRQ1 Sets wait mode

SIO0WRQ0

0: Setting prohibited

1: 1 count

2: 2 counts 3: 3 counts 4: 4 counts

5: 5 counts 6: 6 counts 7: 7 counts

8: 8 counts 9: 9 counts A: 10 counts

B: 11 counts C: 12 counts D: 13 counts

E: 14 counts F: 15 coounts

16-bit

High-order

Low-order

transfer 8-bit transfer 8-bit transfer

0011

93.75

375

281.25

46.875

kHz

0101

7th

8th

7th clock

Stop

clock

after start

condition

Data

Acknowledge

Address

wait

UPD17708 Datasheet(PDF) 71 Page - NEC

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