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UPD17708 Datasheet(PDF) 13 Page - NEC |
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UPD17708 Datasheet(HTML) 13 Page - NEC |
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13 / 356 page ![]() 13 µPD17704, 17705, 17707, 17708, 17709 Pin No. Symbol Function Output Form 30 VDD1 Power supply. Supply the same voltage to these pins. – 79 VDD0 • With CPU and peripheral function operating: 4.5 to 5.5 V • With CPU operating : 3.5 to 5.5 V • With clock stopped : 2.2 to 5.5 V 31 VCOH PLL local oscillation (VCO) frequency input. – 32 VCOL • VCOH • Active with VHF mode selected by program; otherwise, pulled down. • VCOL • Active with HF or MW mode selected by program; otherwise, pulled down. Because the input of these pins goes into an AC amplifier, cut the DC component of the input signal with a capacitor. 34 EO0 Output from charge pump of PLL frequency synthesizer. Outputs the divided CMOS 35 EO1 frequency of local oscillation and the result of comparison of the phase 3-state difference of reference frequency. At reset With clock stopped Power-ON reset WDT&SP reset CE reset High-impedance High-impedance High-impendance High-impedance output output output output 36 TEST Test input pin. – Be sure to connect this pin to GND. 37 P1D3 Port 1D and BEEP output. CMOS 38 P1D2 • P1D3 through P1D0 push-pull 39 P1D1/BEEP1 • 4-bit I/O port 40 P1D0/BEEP0 • Can be set in input or output mode in 1-bit units. • BEEP1, BEEP0 • BEEP output At reset With clock stopped Power-ON reset WDT&SP reset CE reset Input Input Retained Retained (P1D3 through P1D0) (P1D3 through P1D0) (P1D3 through P1D0) (P1D3 through P1D0) 43 P2B3 4-bit I/O Port. CMOS | | Can be set in input or output mode in 1-bit units. push-pull 46 P2B0 At reset With clock stopped Power-ON reset WDT&SP reset CE reset Input Input Retained Retained 47 P3C3 4-bit I/O Port. CMOS | | Can be set in input or output mode in 4-bit units. push-pull 50 P3C0 At reset With clock stopped Power-ON reset WDT&SP reset CE reset Input Input Retained Retained |
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