UPD17708 datasheet(88/356 Pages) NEC

88 / 356 page

µPD17704, 17705, 17707, 17708, 17709

Table 9-1. Relationships between Peripheral Hardware and Data Buffer (1/2)

Peripheral Hardware

Peripheral Register Transferring Data with Data Buffer

Name

Symbol

Peripheral

Execution of

I/O

Actual

address

PUT/GET

bit

instruction

A/D converter

A/D converter reference

ADCR

02H

PUT/GET

voltage setting register

Serial interface

Serial interface 0

Presettable shift register 0

SIO0SFR

03H

PUT/GET

Serial interface 1

Presettable shift register 1

SIO1SFR

04H

Timer 0

Timer 0 modulo register

TM0M

1AH

PUT/GET

Timer 0 counter

TM0C

1BH

GET

Timer 1

Timer 1 modulo register

TM1M

1CH

PUT/GET

Timer 1 counter

TM1C

1DH

GET

Timer 2

Timer 2 modulo register

TM2M

1EH

PUT/GET

Timer 2 counter

TM2C

1FH

GET

Address register

40H

PUT/GET

Data buffer stack

DBF stack

DBFSTK

41H

PUT/GET

PLL frequency synthesizerNote

PLL data register

PLLR

42H

PUT/GET

Frequency counter

IF counter data register

IFC

43H

GET

D/A converter

P1B0/PWM0 pin

PWM data register 0

PWMR0

44H

PUT/GET

(PWM output)

P1B1/PWM1 pin

PWM data register 1

PWMR1

45H

P1B2/PWM2 pin

PWM data register 2

PWMR2

46H

PUT/GET

Timer 3

Timer 3 modulo register

TM3M

Note

The programmable counter of the PLL frequency synthesizer is configured of 17 bits, of which the high-

order 16 bits indicate the PLL data register (PLLR) and the low-order bits are allocated to the PLLSCNF

flag (the third bit of address 10H).

For details, refer to 17. PLL FREQUENCY SYNTHESIZER.

UPD17708 Datasheet(PDF) 88 Page - NEC

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