UPD17708 datasheet(11/356 Pages) NEC

11 / 356 page

µPD17704, 17705, 17707, 17708, 17709

1. PIN FUNCTIONS

1.1 Pin Function List

Pin No.

Symbol

Function

Output Form

INT2

Edge-detectable vectored interrupt input pins. Rising or falling edge can be

–

INT1

specified.

INT0

P1A3/INT4

Port 1A multiplexed with external interrupt request signal input and event

–

P1A2/INT3

signal input pins.

P1A1

• P1A3 through P1A0

P1A0/TM0G

• 4-bit input port

• INT4, INT3

• Edge-detectable vectored interrupt

• TM0G

• Input for gate of 8-bit timer 0

At reset

With clock stopped

Power-ON reset

WDT&SP reset

CE reset

Input

Retained

(P1A3 through P1A0)

P3A3

4-bit I/O port.

CMOS

Can be set in input or output mode in 4-bit units.

push-pull

P3A0

At reset

With clock stopped

Power-ON reset

WDT&SP reset

CE reset

Input

Retained

P3B3

4-bit I/O port.

CMOS

Can be set in input or output mode in 4-bit units.

push-pull

P3B0

At reset

With clock stopped

Power-ON reset

WDT&SP reset

CE reset

Input

Retained

P2A2

Port 2A multiplexed with external gate counter input pins.

CMOS

P2A1/FCG1

• P2A2 through P2A0

push-pull

P2A0/FCG0

• 3-bit I/O port

• Can be set in input or output mode in 1-bit units.

• FCG1, FCG0

• Input for external gate counter

At reset

With clock stopped

Power-ON reset

WDT&SP reset

CE reset

Input

Retained

(P2A2 through P2A0)

UPD17708 Datasheet(PDF) 11 Page - NEC

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