UPD17708 datasheet(201/356 Pages) NEC

201 / 356 page

201

µPD17704, 17705, 17707, 17708, 17709

14.6 Cautions on Using A/D Converter

14.6.1 Cautions on selecting A/D converter pin

When one of the P0D0/AD0 through P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins is selected, the other five

pins are forcibly set in the input port mode. The P0D0/AD0 through P0D3/AD3 pins can be connected to a pull-

down resistor if so specified by the P0DPL0 through P0DPLD3 flags in bank 15. To use the P0D0/AD0 through

P0D3/AD3 pins for the A/D converter, therefore, disconnect their pull-down resistors to correctly detect an

external input analog voltage.

14.7 Status at Reset

14.7.1 At power-ON reset

All the P0D0/AD0 through P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins are set in the general-purpose input

port mode.

The P0D0 through P0D3 pins are connected with a pull-down resistor.

14.7.2 At WDT&SP reset

All the P0D0/AD0 through P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins are set in the general-purpose input

port mode.

The P0D0 through P0D3 pins are connected with a pull-down resistor.

14.7.3 At CE reset

The status of the pin selected for the A/D converter is retained as is.

The previous status of the pull-down resistor of the P0D0 through P0D3 pins is retained.

14.7.4 On execution of clock stop instruction

The status of the pin selected for the A/D converter is retained as is.

The previous status of the pull-down resistor of the P0D0 through P0D3 pins is retained.

14.7.5 In halt status

The status of the pin selected for the A/D converter is retained as is.

The previous status of the pull-down resistor of the P0D0 through P0D3 pins is retained.

UPD17708 Datasheet(PDF) 201 Page - NEC