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COP8TAB5 Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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COP8TAB5 Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 54 page  10.0 Functional Description (Continued) 10.7 CONTROL REGISTERS 10.7.1 CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 7 Bit 0 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1C0 Timer T1 Start/Stop control in timer modes 1 and 2. T1 Underflow Interrupt Pending Flag in timer mode 3 MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively IEDG External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) 10.7.2 PSW Register (Address X'00EF) HC C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 7 Bit 0 The PSW register contains the following select bits: HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable (enables interrupts) The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and RC (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. 10.7.3 ICNTRL Register (Address X'00E8) Unused LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 7 Bit 0 The ICNTRL register contains the following bits: LPEN L/C Port Interrupt Enable (Multi-Input Wake-Up/Interrupt) T0PND Timer T0 Interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge T1ENB Timer T1 Interrupt Enable for T1B Input capture edge 10.7.4 ITMR Register (Address X'00CF) RSVD ITSEL2 ITSEL1 ITSEL0 Bit 7 Bit 0 The ITMR register contains the following bits: RSVD These bits are reserved and must be 0. ITSEL2 Idle Timer period select bit. ITSEL1 Idle Timer period select bit. ITSEL0 Idle Timer period select bit. 11.0 Timers The device contains a very versatile set of timers (T0 and T1). Timer T1 and associated autoreload/capture registers power up containing random data. 11.1 TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE Timer T0, which is a 16-bit timer. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The clock to the IDLE Timer is the instruction cycle clock (one-tenth of the CKI frequency). In addition to its time base function, the Timer T0 supports the following functions: • Exit out of the Idle Mode (See Idle Mode description) • WATCHDOG logic (See WATCHDOG description) • Start up delay out of the HALT mode • Start up delay from POR is a functional block diagram showing the structure of the IDLE Timer and its associated interrupt logic. Bits 11 through 15 of the ITMR register can be selected for triggering the IDLE Timer interrupt. Each time the selected bit underflows (every 4k, 8k, 16k, 32k or 64k selected clocks), the IDLE Timer interrupt pending bit T0PND is set, thus generating an interrupt (if enabled), and bit 6 of the Port G data register is reset, thus causing an exit from the IDLE mode if the device is in that mode. In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the GIE (Global Interrupt Enable) bit must also be set. The T0PND flag and T0EN bit are bits 5 and 4 of the ICNTRL register, respec- tively. The interrupt can be used for any purpose. Typically, it is used to perform a task upon exit from the IDLE mode. For more information on the IDLE mode, refer to Section 12.2 IDLE MODE. The Idle Timer period is selected by bits 0–2 of the ITMR register Bit 3 of the ITMR Register is reserved and should not be used as a software flag. Bits 4 through 7 of the ITMR Register are reserved and must be zero. TABLE 6. Idle Timer Window Length ITSEL2 ITSEL1 ITSEL0 Idle Timer Period 0 0 0 4,096 inst. cycles 0 0 1 8,192 inst. cycles 0 1 0 16,384 inst. cycles 0 1 1 32,768 inst. cycles 1 0 0 65,536 inst. cycles www.national.com 18 |
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