COP8TAB5 datasheet(34/54 Pages) NSC

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15.0 MICROWIRE/PLUS (Continued)

mode may cause the current SK clock for the SIO shift

be set when the input SK clock is in the idle phase.

15.2 MICROWIRE/PLUS MASTER MODE OPERATION

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register. In the slave mode, the shift clock

stops after 8 clock pulses. Table 12 summarizes the bit

settings required for Master mode of operation.

15.3 MICROWIRE/PLUS SLAVE MODE OPERATION

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and

resetting the appropriate bits in the Port G configuration

the Slave mode of operation.

This table assumes that the control flag MSEL is set.

TABLE 12. MICROWIRE/PLUS Mode Settings

G4 (SO)

G5 (SK)

Operation

Config. Bit

Fun.

Int.

MICROWIRE/PLUS

Master

TRI-

Int.

MICROWIRE/PLUS

STATE

Master

Ext.

MICROWIRE/PLUS

Slave

TRI-

Ext.

MICROWIRE/PLUS

STATE

Slave

The user must set the BUSY flag immediately upon entering

the Slave mode. This ensures that all data bits sent by the

Master is shifted properly. After eight clock pulses the BUSY

flag is clear, the shift clock is stopped, and the sequence

may be repeated.

15.4 ALTERNATE SK PHASE OPERATION AND SK

IDLE POLARITY

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK idle polarity can be either high or low.

The polarity is selected by bit 5 of Port G data register. In the

normal mode data is shifted in on the rising edge of the SK

clock and the data is shifted out on the falling edge of the SK

clock. The SIO register is shifted on each falling edge of the

SK clock. In the alternate SK phase operation, data is shifted

in on the falling edge of the SK clock and shifted out on the

rising edge of the SK clock. Bit 6 of Port G configuration

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configu-

ration bit. The SKSEL flag will power up in the reset condi-

tion, selecting the normal SK signal.

20091737

FIGURE 24. MICROWIRE/PLUS Application

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