COP8TAB5 datasheet(31/54 Pages) NSC

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13.0 Interrupts (Continued)

SERVICE:

; Interrupt Service Routine

RBIT,EXPND,PSW

; Reset ext interrupt pend. bit

RET I

; Return, set the GIE bit

13.5 PORT C AND PORT L INTERRUPTS

Ports C and L provides the user with an additional sixteen

fully selectable, edge sensitive interrupts which are all vec-

tored into the same service subroutine.

The interrupt from Ports C and L share logic with the

wake-up circuitry. The registers CWKEN and LWKEN allow

interrupts from Ports C and L to be individually enabled or

disabled. The register CWKEDG and LWKEDG specify the

trigger condition to be either a positive or a negative edge.

Finally, the registers CWKPND and LWKPND latch in the

pending trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port C and Port L interrupts. Setting the LPEN flag will

enable interrupts and vice versa. A separate global pending

flag is not needed since the registers CWKPND and LWK-

PND are adequate.

Since Ports C and L are also used for waking the device out

of the HALT or IDLE modes, the user can elect to exit the

HALT or IDLE modes either with or without the interrupt

enabled. If he elects to disable the interrupt, then the device

will restart execution from the instruction immediately follow-

ing the instruction that placed the microcontroller in the

HALT or IDLE modes. In the other case, the device will first

execute the interrupt service routine and then revert to nor-

mal operation.

13.6 INTERRUPT SUMMARY

The device uses the following types of interrupts, listed

below in order of priority:

The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a re-start procedure.

Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device.

Under ordinary conditions, a maskable interrupt will not

interrupt any other interrupt routine in progress. A

maskable interrupt routine in progress can be inter-

rupted by the non-maskable interrupt request. A

maskable interrupt routine should end with an RETI

instruction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routines if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

While executing from the Boot ROM for ISP or virtual E2

operations, the hardware will disable interrupts from oc-

curring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when

execution is returned to ROM Memory. Subsequent in-

terrupts, during ISP operation, from the same interrupt

source will be lost.

14.0 WATCHDOG/Clock Monitor

The devices contain a user selectable WATCHDOG and

clock monitor. The following section is applicable only if

WATCHDOG feature has been selected in the Option Byte.

The WATCHDOG is designed to detect the user program

getting stuck in infinite loops resulting in loss of program

control or “runaway” programs.

The WATCHDOG logic contains two separate service win-

dows. While the user programmable upper window selects

the WATCHDOG service time, the lower window provides

protection against an infinite program loop that contains the

WATCHDOG service instruction.

The COP8TAx devices provide the added feature of a soft-

ware trap that provides protection against stack overpops

and addressing locations outside valid user program space.

The Clock Monitor is used to detect the absence of a clock or

a very slow clock below a specified rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 8 shows the WDSVR register.

TABLE 8. WATCHDOG Service Register (WDSVR)

Window

Key Data

Clock

Select

Monitor

01100

The lower limit of the service window is fixed at 256 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 9 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

TABLE 9. WATCHDOG Service Window Select

WDSVR WDSVR

Clock

Service Window

Bit 7

Bit 6

Monitor

(Lower-Upper Limits)

256–8k t

C Cycles

256–16k t

C Cycles

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