COP8TAB5 datasheet(43/54 Pages) NSC

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18.0 Instruction Set (Continued)

18.4.3 Load and Exchange Instructions

The load and exchange instructions write byte values in

registers or memory. The addressing mode determines the

source of the data.

Load (LD)

Load Accumulator Indirect (LAID)

Exchange (X)

18.4.4 Logical Instructions

The logical instructions perform the operations AND, OR,

and XOR (Exclusive OR). Other logical operations can be

performed by combining these basic operations. For ex-

ample, complementing is accomplished by exclusive-ORing

the Accumulator with FF Hex.

Logical AND (AND)

Logical OR (OR)

Exclusive OR (XOR)

18.4.5 Accumulator Bit Manipulation Instructions

The Accumulator bit manipulation instructions allow the user

to shift the Accumulator bits and to swap its two nibbles.

Rotate Right Through Carry (RRC)

Rotate Left Through Carry (RLC)

Swap Nibbles of Accumulator (SWAP)

18.4.6 Stack Control Instructions

Push Data onto Stack (PUSH)

Pop Data off of Stack (POP)

18.4.7 Memory Bit Manipulation Instructions

The memory bit manipulation instructions allow the user to

set and reset individual bits in memory.

Set Bit (SBIT)

Reset Bit (RBIT)

Reset Pending Bit (RPND)

18.4.8 Conditional Instructions

The conditional instruction test a condition. If the condition is

true, the next instruction is executed in the normal manner; if

the condition is false, the next instruction is skipped.

If Equal (IFEQ)

If Not Equal (IFNE)

If Greater Than (IFGT)

If Carry (IFC)

If Not Carry (IFNC)

If Bit (IFBIT)

If B Pointer Not Equal (IFBNE)

And Skip if Zero (ANDSZ)

Decrement Register and Skip if Zero (DRSZ)

18.4.9 No-Operation Instruction

The no-operation instruction does nothing, except to occupy

space in the program memory and time in execution.

No-Operation (NOP)

Note: The VIS is a special case of the Indirect Transfer of

Control addressing mode, where the double byte vector

associated with the interrupt is transferred from adjacent

addresses in the program memory into the program counter

(PC) in order to jump to the associated interrupt service

routine.

18.5 REGISTER AND SYMBOL DEFINITION

The following abbreviations represent the nomenclature

used in the instruction description and the COP8 cross-

assembler.

Registers

8-Bit Accumulator Register

8-Bit Address Register

8-Bit Segment Register

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Lower 8 Bits of PC

1 Bit of PSW Register for Carry

1 Bit of PSW Register for Half Carry

GIE

1 Bit of PSW Register for Global Interrupt

Enable

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Symbols

[B]

Memory Indirectly Addressed by B Register

[X]

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Mem

Direct Addressed Memory or [B]

Meml

Direct Addressed Memory or [B] or

Immediate Data

Imm

8-Bit Immediate Data

Reg

(Includes B, X and SP)

Bit

Bit Number (0 to 7)

←

Loaded with

↔

Exchanged with

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