COP8TAB5 datasheet(9/54 Pages) NSC

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8.0 Electrical Characteristics (Continued)

AC Electrical Characteristics −40˚C

≤ T

A ≤ +85˚C unless otherwise

specified.

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

Crystal/Resonator, External

2.25V

≤ V

≤ 2.75V

0.65

µs

Internal R/C Oscillator

2.25V

≤ V

≤ 2.75V

1.0

µs

R/C Oscillator Frequency Variation

2.25V

≤ V

≤ 2.75V

±30

External CKI Clock Duty Cycle

fr = Max

Rise Time

fr = 10 MHz Ext Clock

Fall Time

fr = 10 MHz Ext Clock

Inputs

MICROWIRE Setup Time (t

UWS)20

MICROWIRE Hold Time (t

UWH)20

MICROWIRE Output Propagation Delay (t

UPD)

150

MICROWIRE Maximum Shift Clock

Master Mode

750

kHz

Slave Mode

1.5

MHz

Input Pulse Width

Interrupt Input High Time (see (Note 2))

Interrupt Input Low Time

Timer Input High Time

Timer Input Low Time

ACCESS.Bus Input signals (see (Note 6))

Bus Free Time Between Stop and Start Condition

BUFi)

SCLhigho

SCL Setup Time (t

CSTOsi)

Before Stop Condition

mclk

SCL Hold Time (t

CSTRhi)

After Start Condition

mclk

SCL Setup Time (t

CSTRsi)

Before Start Condition

mclk

Data High Setup Time (t

DHCsi)

Before SCL Rising Edge

(RE)

mclk

Data Low Setup Time (t

DLCsi)

Before SCL RE

mclk

SCL Low Time (t

SCLlowi)

After SCL Falling Edge (FE)

mclk

SCL High Time (t

SCLhighi)

After SCL RE

mclk

SDA Hold Time (t

SDAhi)

After SCL FE

SDA Setup Time (t

SDAsi)

Before SCL RE

mclk

ACCESS.Bus Output Signals (see(Note 6))

Bus Free Time Between Stop and Start Condition

BUFo)

SCLhigho

SCL Setup Time (t

CSTOso)

Before Stop Condition

SCLhigho

SCL Hold Time (t

CSTRho)

After Start Condition

SCLhigho

SCL Setup Time (t

CSTRso)

Before Start Condition

SCLhigho

Data High Setup Time (t

DHCso

Before SCL RE

SCLhigho

Data Low Setup Time (t

DLCso)

Before SCL RE

SCLhigho

SCL Low Time (t

SCLlowo)

After SCL FE

mclk

SCL High Time (t

SCLhigho)

After SCL RE

mclk

SDA Hold Time (t

SDAho)

After SCL FE

mclk

SDA Valid Time (t

SDAso)

Before SCL FE

mclk

Note 2: tC = Instruction cycle time (Clock input frequency divided by 10).

Note 3: Maximum rate of voltage change must be < 0.5 V/ms.

COP8TAB5 Datasheet(PDF) 9 Page - National Semiconductor (TI)

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