COP8TAB5 datasheet(38/54 Pages) NSC

38 / 54 page

16.0 ACCESS.Bus Interface

(Continued)

16.5 ACB SERIAL DATA REGISTER (ACBSDA)

The ACBSDA register is a byte-wide, read/write shift register

used to transmit and receive data. The most significant bit is

transmitted (received) first and the least significant bit is

transmitted (received) last.

DATA

16.6 ACB STATUS REGISTER (ACBST)

The ACBST register is a byte-wide, read-only register that

reports the current ACB status.

SLVSTP SDAST BER NEGACK RSVD NMATCH MASTER XMIT

SLVSTP

The Slave Stop bit is set when a Stop

Condition was detected after a slave transfer

(i.e., after a slave transfer in which MATCH

or GCMTCH is set).

SDAST

The SDA Status bit is set when the SDA

data register is waiting for data (transmit, as

master or slave) or holds data that should be

read (receive, as master or slave)

BER

The Bus Error bit is set when a Start or Stop

Condition is detected during data transfer or

when an arbitration problem is detected.

NEGACK

The Negative Acknowledge bit is set when a

transmission is not acknowledged.

RSVD

This bit is reserved and will be zero.

NMATCH

The New Match bit is set when the address

byte following a Start Condition, or repeated

starts, causes a match or a global-call

match.

MASTER

The Master bit indicates that the module is

currently in master mode. It is set when a

request for bus mastership succeeds. It is

cleared upon arbitration loss (BER is set) or

the recognition of a Stop Condition.

XMIT

The Direction bit is set when the ACB

module is currently in master/slave transmit

mode. Otherwise, it is clear.

16.7 ACB CONTROL STATUS REGISTER (ACBCST)

The ACBCST register is a byte-wide, read/write register that

reports the current ACB status. At reset and when the mod-

ule is disabled, the non-reserved bits of ACBCST are

cleared.

543

RSVD

TGSCL

TSDA

GCMTCH MATCH BB BUSY

TGSCL

The Toggle SCL bit enables toggling the SCL

signal during error recovery. When the SDA

signal is low, writing 1 to this bit drives the

SCL signal high for one cycle. Writing 1 to

TGSCL when the SDA signal is high is

ignored.

TSDA

The Test SDA bit samples the state of the

SDA signal. This bit can be used while

recovering from an error condition in which

the SDA signal is constantly pulled low by a

slave that has lost synchronization. This bit is

a read-only bit.

GCMTCH

The Global Call Match bit is set in slave

mode when the ACBCTL1.GCMEN bit is set

and the address byte (the first byte

transferred after a Start Condition) is 00.

MATCH

The Address Match bit indicates in slave

mode when ACBADDR.SAEN is set and the

first seven bits of the address byte (the first

byte transferred after a Start Condition)

matches the 7-bit address in the ACBADDR

The Bus Busy bit indicates the bus is busy. It

is set when the bus is active (i.e., a low level

on either SDA or SCL) or by a Start

Condition. It is cleared when the module is

disabled or a Stop Condition is detected.

BUSY

The BUSY bit indicates that the ACB module

is:

•

Generating a Start Condition

•

In Master mode (ACBST.MASTER is set)

•

Slave

mode

(ACBCST.MATCH

ACBCST.GCMTCH is set)

•

In the period between detecting a Start and

completing the reception of the address

byte. After this, the ACB either becomes

not busy or enters slave mode. The BUSY

bit is cleared by the completion of any of

the above states, or by disabling the

module. BUSY is a read only bit.

16.8 ACB CONTROL 1 REGISTER (ACBCTL1)

The ACBCTL1 register is a byte-wide, read/write register

that configures and controls the ACB module. At reset and

while the module is disabled (ACBCTL2.ENABLE = 0), the

ACBCTL1 register is cleared.

CLRST NMINTE GCMEN ACK RSVD

INTEN

STOP

START

CLRST

The Clear Status bit clears the NMATCH,

BER, NEGACK and SLVSTP bits when 1 is

written to this bit.

NMINTE

The New Match Interrupt Enable controls

whether ACB interrupts are generated on

new matches.

COP8TAB5 Datasheet(PDF) 38 Page - National Semiconductor (TI)

COP8TAB5 Datasheet(HTML) 38 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Descarga

Enlace URL