COP8TAB5 datasheet(19/54 Pages) NSC

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11.0 Timers (Continued)

TABLE 6. Idle Timer Window Length (Continued)

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

Reserved - Undefined

The ITSEL bits of the ITMR register are cleared on Reset

and the Idle Timer period is reset to 4,096 instruction cycles.

11.1.1 ITMR Register

RSVD

ITSEL2 ITSEL1 ITSEL0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSVD: These bits are reserved and must be set to 0.

ITSEL2:0: Selects the Idle Timer period as described in

Table 6

Any time the IDLE Timer period is changed there is the

possibility of generating a spurious IDLE Timer interrupt by

setting the T0PND bit. The user is advised to disable IDLE

Timer interrupts prior to changing the value of the ITSEL bits

of the ITMR Register and then clear the T0PND bit before

attempting to synchronize operation to the IDLE Timer.

11.2 TIMER T1

One of the main functions of a microcontroller is to provide

timing and counting capability for real-time control tasks. The

COP8 family offers a very versatile 16-bit timer/counter

structure, and two supporting 16-bit autoreload/capture reg-

isters (R1A and R1B), optimized to reduce software burdens

in real-time control applications. The timer block has two pins

associated with it, T1A and T1B. Pin T1A supports I/O re-

quired by the timer block, while pin T1B is an input to the

timer block.

The timer block has three operating modes: Processor Inde-

pendent PWM mode, External Event Counter mode, and

Input Capture mode.

The control bits T1C3, T1C2, and T1C1 allow selection of the

different modes of operation.

11.3 MODE 1. PROCESSOR INDEPENDENT PWM

MODE

One of the timer’s operating modes is the Processor Inde-

pendent PWM mode. In this mode, the timer generates a

“Processor Independent” PWM signal because once the

timer is setup, no more action is required from the CPU

which translates to less software overhead and greater

throughput. The user software services the timer block only

when the PWM parameters require updating. This capability

is provided by the fact that the timer has two separate 16-bit

reload registers. One of the reload registers contains the

“ON” timer while the other holds the “OFF” time. By contrast,

a microcontroller that has only a single reload register re-

quires an additional software to update the reload value

(alternate between the on-time/off-time).

The timer can generate the PWM output with the width and

duty cycle controlled by the values stored in the reload

registers. The reload registers control the countdown values

and the reload values are automatically written into the timer

when it counts down through 0, generating interrupt on each

reload. Under software control and with minimal overhead,

the PMW outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acqui-

sition and sine wave generators.

In this mode, the timer T1 counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, R1A and R1B. The very

first underflow of the timer causes the timer to reload from

the register R1A. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the

timer for PWM mode operation.

Figure 15 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the T1A output

pin. The underflows can also be programmed to generate

interrupts.

Underflows from the timer are alternately latched into two

pending flags, T1PNDA and T1PNDB. The user must reset

these pending flags under software control. Two control

enable flags, T1ENA and T1ENB, allow the interrupts from

the timer underflow to be enabled or disabled. Setting the

timer enable flag T1ENA will cause an interrupt when a timer

underflow causes the R1A register to be reloaded into the

timer. Setting the timer enable flag T1ENB will cause an

interrupt when a timer underflow causes the R1B register to

be reloaded into the timer. Resetting the timer enable flags

will disable the associated interrupts.

Either or both of the timer underflow interrupts may be

enabled. This gives the user the flexibility of interrupting

once per PWM period on either the rising or falling edge of

the PWM output. Alternatively, the user may choose to inter-

rupt on both edges of the PWM output.

11.4 MODE 2. EXTERNAL EVENT COUNTER MODE

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, T1, is clocked by the input signal from the T1A pin. The

T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer

to be clocked either on a positive or negative edge from the

T1A pin. Underflows from the timer are latched into the

T1PNDA pending flag. Setting the T1ENA control flag will

cause an interrupt when the timer underflows.

In this mode the input pin T1B can be used as an indepen-

dent positive edge sensitive interrupt input if the T1ENB

control flag is set. The occurrence of a positive edge on the

T1B input pin is latched into the T1PNDB flag.

20091731

FIGURE 15. Timer in PWM Mode

COP8TAB5 Datasheet(PDF) 19 Page - National Semiconductor (TI)

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