COP8TAB5 datasheet(37/54 Pages) NSC

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16.0 ACCESS.Bus Interface

(Continued)

At each clock cycle, the slave can stall the master while it

handles the previous data, or prepares new data. The slave

can hold SCL low, to extend the clock-low period, on each bit

transfer, or on a byte boundary, to accomplish this. Typically,

slaves extend the first clock cycle of a transfer if a byte read

has not yet been stored, or if the next byte to be transmitted

is not yet ready. Some microcontrollers, with limited hard-

ware support for ACCESS.Bus, extend the access after each

bit, to allow software time to handle this bit.

16.1.1 Start and Stop

The ACCESS.Bus master generates Start and Stop Condi-

tions (control codes). After a Start Condition is generated,

the bus is considered busy and it retains this status until a

certain time after a Stop Condition is generated. A high-to-

low transition of the data line (SDA) while the clock (SCL) is

high indicates a Start Condition. A low-to-high transition of

the SDA line while the SCL is high indicates a Stop Condition

(Figure 30).

In addition to the first Start Condition, a repeated Start

Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a change in

the direction of the data transfer.

16.1.2 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the ac-

knowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiv-

ing device.

The master generates an acknowledge clock pulse after

each byte transfer. The receiver sends an acknowledge

signal after every byte received. There are two exceptions to

the "acknowledge after every byte" rule.

•

When the master is the receiver, it must indicate to the

transmitter

end-of-data

condition

not-

acknowledging ("negative acknowledge") the last byte

clocked out of the slave. This "negative acknowledge"

still includes the acknowledge clock pulse (generated by

the master), but the SDA line is not pulled down.

•

When the receiver is full, otherwise occupied, or a prob-

lem has occurred, it sends a negative acknowledge to

indicate that it cannot accept additional data bytes.

16.1.3 Addressing Transfer Formats

Each device on the bus has a unique address. Before any

data is transmitted, the master transmits the address of the

slave being addressed. The slave device should send an

acknowledge signal on the SDA signal, once it recognizes its

address.

16.2 BUS ARBITRATION

Arbitration is required when multiple master devices attempt

to gain control of the bus simultaneously. Control of the bus

is initially determined according to the address bits and clock

cycle. If the masters are trying to address the same bus

device, data comparisons determine the outcome of this

arbitration. In master mode, the device immediately aborts a

transaction if the value sampled on the SDA line differs from

the value driven by the device.

When an abort occurs during the address transmission, the

master that identifies the conflict should give up the bus,

switch to slave mode, and continue to sample SDA to see if

it is being addressed by the winning master on the

ACCESS.Bus.

16.3 POWER SAVE MODES

When this device is placed in HALT or IDLE mode, the ACB

module is effectively disabled. Registers ACBST, ACBCST

and ACBCTL1 are reset, however ACBSDA, ACBADDR and

ACBCTL2

are

unaffected.

the

ACB

enabled

(ACBCTL2.ENABLE = 1) on detection of a Start Condition, a

wake-up signal is issued to the Multi-Input Wake-Up module.

The byte transfer which causes the Wake-Up event will not

be acknowledged by the COP8 ACCESS.Bus and thus must

be retransmitted. The Multi-Input Wake-Up logic must be

configured, by the user, to enable Wake-Up on ACCESS.Bus

transfer. The ACCESS.Bus SDA signal is an alternate func-

tion of the one of the Multi-Input Wake-Up pins, and thus the

associated bit of the LWKEN or CWKEN and LWKEDG or

CWKEDG registers must be configured to cause a Wake-Up

event on a rising edge. See Figure 20 and the pinout table

for determination of the Multi-Input Wake-Up channel asso-

ciated with the ACCESS.Bus.

16.4 SDA AND SCL DRIVER CONFIGURATION

SDA and SCL are driven as open-drain signals on Port L

signals L0 and L1. If the ACB interface is not being used,

these pins are available for use as general-purpose port pins

or Multi-Input Wake-Up inputs.

20091780

FIGURE 30. Start and Stop Conditions

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