COP8TAB5 datasheet(13/54 Pages) NSC

No. de pieza	COP8TAB5

Descripción Electrónicos	8-Bit CMOS ROM Microcontroller with 2k or 4k Memory

PDF	54 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NSC [National Semiconductor (TI)]

Página de inicio	http://www.national.com

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13 / 54 page

9.0 Pin Descriptions (Continued)

L3 Multi-Input Wake-Up

L2 Multi-Input Wake-Up (optional 1.8V compatible input)

L1 Multi-Input Wake-Up or ACCESS.Bus Serial Clock (op-

tional 1.8V compatible input)

L0 Multi-Input Wake-Up or ACCESS.Bus Serial Data (op-

tional 1.8V compatible input)

10.0 Functional Description

The architecture of the device is a modified Harvard archi-

tecture. With the Harvard architecture, the program memory

(ROM) is separate from the data store memory (RAM). Both

Program Memory and Data Memory have their own separate

addressing space with separate address buses. The archi-

tecture, though based on the Harvard architecture, permits

transfer of data from ROM Memory to RAM.

10.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

C) cycle time.

20091760

FIGURE 6. I/O Port Configurations

20091761

FIGURE 7. I/O Port Configurations — Output Mode

20091762

FIGURE 8. I/O Port Configurations — Input Mode

COP8TAB5 Datasheet(PDF) 13 Page - National Semiconductor (TI)