S25FL256SDPNFAQ datasheet(32/149 Pages) CYPRESS

32 / 149 page

Document Number: 001-98283 Rev. *M

Page 31 of 148

S25FL128S/S25FL256S

5.4

SDR AC Characteristics

Notes:

1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.

2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.

3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.

4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.

5. ±10% duty cycle is supported for frequencies

 50 MHz.

6. Maximum value only applies during Program/Erase Suspend/Resume commands.

Table 12. AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V)

Symbol

Parameter

Min

Typ

Max

Unit

FSCK, R

SCK Clock Frequency for READ and 4READ

instructions

MHz

FSCK, C

SCK Clock Frequency for single commands as

shown in Table 45 on page 67 (4)

133

MHz

FSCK, C

SCK Clock Frequency for the following dual and

quad commands: DOR, 4DOR, QOR, 4QOR,

DIOR, 4DIOR, QIOR, 4QIOR

104

MHz

FSCK, QPP

SCK Clock Frequency for the QPP, 4QPP

commands

MHz

PSCK

SCK Clock Period

1/ FSCK



tWH, tCH

Clock High Time (5)

45% PSCK

tWL, tCL

Clock Low Time (5)

45% PSCK

tCRT, tCLCH Clock Rise Time (slew rate)

0.1

V/ns

tCFT, tCHCL Clock Fall Time (slew rate)

0.1

V/ns

tCS

CS# High Time (Read Instructions)

CS# High Time (Program/Erase)

tCSS

CS# Active Setup Time (relative to SCK)

tCSH

CS# Active Hold Time (relative to SCK)

3000 (6)

tSU

Data in Setup Time

1.5

tHD

Data in Hold Time

Clock Low to Output Valid

8.0 (2)

7.65 (3)

6.5 (4)

tHO

Output Hold Time

tDIS

Output Disable Time

tWPS

WP# Setup Time

20 (1)

tWPH

WP# Hold Time

100 (1)

tHLCH

HOLD# Active Setup Time (relative to SCK)

tCHHH

HOLD# Active Hold Time (relative to SCK)

tHHCH

HOLD# Non Active Setup Time (relative to SCK)

tCHHL

HOLD# Non Active Hold Time (relative to SCK)

tHZ

HOLD# enable to Output Invalid

tLZ

HOLD# disable to Output Valid

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