S25FL256SDPNFAQ datasheet(33/149 Pages) CYPRESS

33 / 149 page

Document Number: 001-98283 Rev. *M

Page 32 of 148

S25FL128S/S25FL256S

Notes:

1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.

2. CL = 30 pF.

3. CL = 15 pF.

4. ±10% duty cycle is supported for frequencies

 50 MHz.

5. Maximum value only applies during Program/Erase Suspend/Resume commands.

Table 13. AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V)

Symbol

Parameter

Min

Typ

Max

Unit

FSCK, R

SCK Clock Frequency for READ, 4READ

instructions

MHz

FSCK, C

SCK Clock Frequency for all others (3)

MHz

PSCK

SCK Clock Period

1/ FSCK



tWH, tCH

Clock High Time (4)

45% PSCK

tWL, tCL

Clock Low Time (4)

45% PSCK

tCRT, tCLCH Clock Rise Time (slew rate)

0.1

V/ns

tCFT, tCHCL Clock Fall Time (slew rate)

0.1

V/ns

tCS

CS# High Time (Read Instructions)

CS# High Time (Program/Erase)

tCSS

CS# Active Setup Time (relative to SCK)

tCSH

CS# Active Hold Time (relative to SCK)

3000 (5)

tSU

Data in Setup Time

tHD

Data in Hold Time

Clock Low to Output Valid

14.5 (2)

12.0 (3)

tHO

Output Hold Time

tDIS

Output Disable Time

tWPS

WP# Setup Time

20 (1)

tWPH

WP# Hold Time

100 (1)

tHLCH

HOLD# Active Setup Time (relative to SCK)

tCHHH

HOLD# Active Hold Time (relative to SCK)

tHHCH

HOLD# Non Active Setup Time (relative to SCK)

tCHHL

HOLD# Non Active Hold Time (relative to SCK)

tHZ

HOLD# enable to Output Invalid

tLZ

HOLD# disable to Output Valid

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