S25FL256SDPNFAQ datasheet(61/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 60 of 148

S25FL128S/S25FL256S

8.3.1

Freeze Bit

Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register 1 and the TBPROT bit

in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once the FREEZE bit has been written to a logic 1

it cannot be cleared to a logic 0 until a power-on-reset is executed. As long as the FREEZE bit is cleared to logic 0 the status register

BP bits and the TBPROT bit of the Configuration Register are writable. The FREEZE bit also protects the entire OTP memory space

from programming when set to 1. Any attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no

error status is set.

8.3.2

Write Protect Signal

The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide hardware input signal

controlled protection. When WP# is Low and SRWD is set to 1 the Status and Configuration register is protected from alteration.

This prevents disabling or changing the protection defined by the Block Protect bits.

8.4

Advanced Sector Protection

Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software methods used to disable or

enable programming or erase operations, individually, in any or all sectors. An overview of these methods is shown in Figure 43

on page 60.

Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for each sector, i.e. if either

mechanism is protecting a sector the sector cannot be programmed or erased. Refer to Section 8.3 Block Protection on page 59 for

full details of the BP2-0 bits.

Figure 43. Advanced Sector Protection Overview

ASP Register

One Time Programmable

Password Method

(ASPR[2]=0)

Persistent Method

(ASPR[1]=0)

64-bit Password

(One Time Protect)

PBB Lock Bit

‘0’ = PPBs locked

Sector 0

Memory Array

Sector N -2

Sector 1

Sector 2

Sector N -1

Sector N

PPB 0

Persistent

Protection Bit

(PPB)

PPB N-2

PPB 1

PPB 2

PPB N-1

PPB N

DYB 0

Dynamic

Protection Bit

(DYB)

DYB N-2

DYB 1

DYB 2

DYB N-1

DYB N

3) DYB are volatile bits

‘1’=PPBs unlocked

Sector 0

Memory Array

Sector N -2

Sector 1

Sector 2

Sector N -1

Sector N

1) N = Highest Address Sector,

a sector is protected if its PPB =’0’

or its DYB = ‘0’

PPB 0

Persistent

Protection Bits

(PPB)

PPB N-2

PPB 1

PPB 2

PPB N-1

PPB N

DYB 0

Dynamic

Protection Bits

(DYB)

DYB N-2

DYB 1

DYB 2

DYB N-1

DYB N

PPB are programmed individually

but erased as a group

4) PPB Lock bit is volatile and

defaults to ‘1’ (persistent mode), or

‘0’ (password mode) upon reset

5) PPB Lock = ‘0’ locks all PPBs

to their current state

6) Password Method requires a

password to set PPB Lock to ‘1’

to enable program or erase of

PPB bits

7) Persistent Method only allows

PPB Lock to be cleared to ‘0’ to

prevent program or erase of PPB

bits. Power off or hardware reset

required to set PPB Lock to ‘1’

S25FL256SDPNFAQ Datasheet(PDF) 61 Page - Cypress Semiconductor

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