S25FL256SDPNFAQ datasheet(23/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

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S25FL128S/S25FL256S

3.3.21 DDR Latency Cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array

before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]).

During the latency cycles, the host keeps RESET# high and CS# low. The host may not drive the IO signals during these cycles. So

that there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between

host and memory when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning

Pattern (DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles

so that there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP.

When there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles of latency.

The next interface state following the last latency cycle is a DDR Single, Dual, or Quad Output Cycle, depending on the instruction.

3.3.22 DDR Single Output Cycle - Memory to Host Transfer

The DDR Fast Read command returns bits to the host only on the SO / IO1 signal. One bit is transferred on the rising edge of SCK

and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The other IO signals are not driven by the

memory.

The next interface state continues to be DDR Single Output Cycle until the host returns CS# to high ending the command.

3.3.23 DDR Dual Output Cycle - Memory to Host Transfer

The DDR Dual I/O Read command returns bits to the host only on the IO0 and IO1 signals. Two bits are transferred on the rising

edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The IO2 and IO3 signals

are not driven by the memory.

The next interface state continues to be DDR Dual Output Cycle until the host returns CS# to high ending the command.

3.3.24 DDR Quad Output Cycle - Memory to Host Transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the rising edge of SCK

and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.

The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the command.

3.4

Configuration Register Effects on the Interface

The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the

number of mode bit and latency cycles for each type of instruction.

The configuration register bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP# and allow Quad Page

Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected to allow Read DDR Quad I/O

commands.

3.5

Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These

are described below. Other software managed protection methods are discussed in the Software Interface on page 44 section of this

document.

3.5.1

Power-Up

When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation. Program and erase operations continue

to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface

Standby state.

3.5.2

Low Power

When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

3.5.3

Clock Pulse Count

The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count that is a multiple of

eight before executing them. A command not having a multiple of 8 clock pulse count is ignored and no error status is set for the

command.

S25FL256SDPNFAQ Datasheet(PDF) 23 Page - Cypress Semiconductor

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