S25FL256SDPNFAQ datasheet(94/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

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S25FL128S/S25FL256S

Figure 9.21 Continuous Quad I/O Read Command Sequence (4-byte Address), LC=00b

9.4.7

DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh)

The instruction



0Dh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or



0Dh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or



0Eh is followed by a 4-byte address (A31-A0)

The DDR Fast Read command improves throughput by transferring address and data on both the falling and rising edge of SCK. It

is similar to the Fast Read command but allows transfer of address and data on every edge of the clock.

The maximum operating clock frequency for DDR Fast Read command is 80 MHz.

For the DDR Fast Read command, there is a latency required after the last address bits are shifted into SI before data begins

shifting out of SO. There are different ordering part numbers that select the latency code table used for this command, either the

High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The HPLC table does not provide cycles

for mode bits so each DDR Fast Read command starts with the 8 bit instruction, followed by address, followed by a latency period.

This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the

dummy cycles, the data value on SI is “don’t care” and may be high impedance. The number of dummy cycles is determined by the

frequency of SCK (Table 28 on page 51). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1).

Then the memory contents, at the address given, is shifted out, in DDR fashion, one bit at a time on each clock edge through SO.

Each bit is shifted out at the SCK frequency by the rising and falling edge of the SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

The EHPLC table does provide cycles for mode bits so a series of DDR Fast Read commands may eliminate the 8 bit instruction

after the first DDR Fast Read command sends a mode bit pattern of complementary first and second Nibbles, e.g. A5h, 5Ah, 0Fh,

etc., that indicates the following command will also be a DDR Fast Read command. The first DDR Fast Read command in a series

starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a latency period. If the mode

bit pattern is complementary the next command is assumed to be an additional DDR Fast Read command that does not provide

instruction bits. That command starts with address, followed by mode bits, followed by latency.

10111213

141516

Data N

Data N+1

32 Bit Address

Mode

Dummy

Data 1

Data 2

2 cycles

8 cycles

2 cycles

4 cycles

2 cycles

CS#

SCK

IO0

IO1

IO2

IO3

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