S25FL256SDPNFAQ datasheet(37/149 Pages) CYPRESS

37 / 149 page

Document Number: 001-98283 Rev. *M

Page 36 of 148

S25FL128S/S25FL256S

5.5.2

DDR Output Timing

Figure 36. SPI DDR Output Timing

Figure 37. SPI DDR Data Valid Window

Notes:

1. tCLH is the shorter duration of tCL or tCH.

2. tO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.

3. tOTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO.

4. tOTT is dependent on system level considerations including:

a. Memory device output impedance (drive strength).

b. System level parasitics on the IOs (primarily bus capacitance).

c. Host memory controller input vIH and vIL levels at which 0 to 1 and 1 to 0 transitions are recognized.

d. As an example, assuming that the above considerations result a memory output slew rate of 2V/ns and a 3V transition (from 1 to 0 or 0 to 1) is required by the host,

the tOTT would be:

tOTT = 3V/(2V/ns) = 1.5 ns

e. tOTT is not a specification tested by Cypress, it is system dependent and must be derived by the system designer based on the above considerations.

5. The minimum data valid window (tDV) can be calculated as follows:

a. As an example, assuming:

i. 80 MHz clock frequency = 12.5 ns clock period

ii. DDR operations are specified to have a duty cycle of 45% or higher

iii. tCLH = 0.45*PSCK = 0.45x12.5 ns = 5.625 ns

iv. tO_SKEW = 600 ps

v. tOTT = 1.5 ns

b. tDV = tCLH - tO_SKEW - tOTT

c. tDV = 5.625 ns - 600 ps - 1.5 ns = 3.525 ns

CS#

SCK

SO_or_IO

MSB

LSB

tCS

tDIS

tLZ

tHO

IO0

IO1

IO2

IO_valid

IO3

tDV

Slow

Fast

tO_SKEW

SCK

Valid

tOTT

tCH

tCL

tDV

Valid

PSCK

S25FL256SDPNFAQ Datasheet(PDF) 37 Page - Cypress Semiconductor

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