S25FL256SDPNFAQ datasheet(88/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 87 of 148

S25FL128S/S25FL256S

9.4.3

Dual Output Read (DOR 3Bh or 4DOR 3Ch)

The instruction



3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or



3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or



3Ch is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO). Two bits are shifted

out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for the Dual Output Read command is 104 MHz. For Dual Output Read commands, there

are zero or eight dummy cycles required after the last address bit is shifted into SI before data begins shifting out of IO0 and IO1.

This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to read from the initial address. During the

dummy cycles, the data value on SI is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the

frequency of SCK (refer to Table 28, Latency Codes for SDR Enhanced High Performance on page 51).

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

Figure 9.11 Dual Output Read Command Sequence (3-byte Address, 3Bh [ExtAdd=0], LC=10b)

Figure 9.12 Dual Output Read Command Sequence (4-byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b])

Figure 61. Dual Output Read Command Sequence (4-byte Address, 3Ch or 3Bh [ExtAdd=1, LC=11b])

CS#

SCK

IO0

IO1

Phase

22 21

Instruction

Address

8 Dummy Cycles

Data 1

Data 2

CS#

SCK

IO0

IO1

Phase

31 30 29

Instruction

Address

8 Dummy Cycles

Data 1

Data 2

CS#

SCK

IO0

IO1

Phase

31 30 29

Instruction

Address

Data 1

Data 2

S25FL256SDPNFAQ Datasheet(PDF) 88 Page - Cypress Semiconductor

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