S25FL256SDPNFAQ datasheet(70/149 Pages) CYPRESS

70 / 149 page

Document Number: 001-98283 Rev. *M

Page 69 of 148

S25FL128S/S25FL256S

9.1.2

Read Device Identification

There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories

from different vendors have used different commands and formats for reading information about the memories. The S25FL128S and

S25FL256S devices support the three most common device information commands.

9.1.3

There are multiple registers for reporting embedded operation status or controlling device configuration options. There are

commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Non-volatile bits in registers

are automatically erased and programmed as a single (write) operation.

9.1.3.1 Monitoring Operation Status

The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the

Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command provides the state of the WIP bit. The

program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether the most recent program or erase

command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating

the device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid

commands. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to

standby state. CLSR clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software

Reset (RESET) may be used to return the device to standby state.

Advanced Sector

Protection

DYBRD

DYB Read

133

DYBWR

DYB Write

133

PPBRD

PPB Read

133

PPBP

PPB Program

133

PPBE

PPB Erase

133

ASPRD

ASP Read

133

ASPP

ASP Program

133

PLBRD

PPB Lock Bit Read

133

PLBWR

PPB Lock Bit Write

133

PASSRD

Password Read

133

PASSP

Password Program

133

PASSU

Password Unlock

133

Reset

RESET

Software Reset

133

MBR

Mode Bit Reset

133

Reserved for

Future Use

MPM

Reserved for Multi-I/O-High Perf Mode (MPM)

133

RFU

Reserved-18 Reserved

RFU

Reserved-E5 Reserved

RFU

Reserved-E6 Reserved

Table 45. S25FL128S and S25FL256S Command Set (sorted by function) (Continued)

Function

Command

Name

Command Description

Instruction

Value (Hex)

Maximum

Frequency

(MHz)

S25FL256SDPNFAQ Datasheet(PDF) 70 Page - Cypress Semiconductor

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