S25FL256SDPNFAQ datasheet(79/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 78 of 148

S25FL128S/S25FL256S

9.3.8

Write Enable (WREN 06h)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to a 1. The Write

Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN) command to enable write, program and erase

commands.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being

driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not

be executed.

Figure 51. Write Enable (WREN) Command Sequence

9.3.9

Write Disable (WRDI 04h)

The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register-1 (SR1[1]) to a 0.

The Write Enable Latch (WEL) bit may be set to a 0 by issuing the Write Disable (WRDI) command to disable Page Program (PP),

Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR), OTP Program (OTPP), and other commands, that require WEL be set

to 1 for execution. The WRDI command can be used by the user to protect memory areas against inadvertent writes that can

possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being

driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write disable operation will not

be executed.

Figure 52. Write Disable (WRDI) Command Sequence

Instruction

SCK

CS#

Instruction

SCK

CS#

S25FL256SDPNFAQ Datasheet(PDF) 79 Page - Cypress Semiconductor