S25FL256SDPNFAQ datasheet(110/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 109 of 148

S25FL128S/S25FL256S

9.6.4

Erase Suspend and Resume Commands (ERSP 75h or ERRS 7Ah)

The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or program data to, any

other sector. Erase Suspend is valid only during a sector erase operation. The Erase Suspend command is ignored if written during

the Bulk Erase operation.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (erase

suspend latency) to suspend the erase operation and update the status bits. See Table 52 on page 120.

Commands allowed after the Erase Suspend command is issued:



Read Status Register 1 (RDSR1 05h)



Read Status Register 2 (RDSR2 07h)

The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the erase operation has stopped. The

Erase Suspend bit in Status Register-2 (SR2[1]) can be used to determine if an erase operation has been suspended or was

completed at the time WIP changes to 0.

If the erase operation was completed during the suspend operation, a resume command is not needed and has no effect if issued.

Erase Resume commands will be ignored unless an Erase operation is suspended.

See Table 49 on page 110 for the commands allowed while erase is suspend.

After the erase operation has been suspended, the sector enters the erase-suspend mode. The system can read data from or

program data to the device. Reading at any address within an erase-suspended sector produces undetermined data.

A WREN command is required before any command that will change non-volatile data, even during erase suspend.

The WRR and PPB Erase commands are not allowed during Erase Suspend, it is therefore not possible to alter the Block Protection

or PPB bits during Erase Suspend. If there are sectors that may need programming during Erase suspend, these sectors should be

protected only by DYB bits that can be turned off during Erase Suspend. However, WRR is allowed immediately following the BRAC

command; in this special case the WRR is interpreted as a write to the Bank Address Register, not a write to SR1 or CR1.

If a program command is sent for a location within an erase suspended sector the program operation will fail with the P_ERR bit set.

After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The system can

determine the status of the program operation by reading the WIP bit in the Status Register, just as in the standard program

operation.

The Erase Resume command 7Ah must be written to resume the erase operation if an Erase is suspend. Erase Resume commands

will be ignored unless an Erase is Suspend.

After an Erase Resume command is sent, the WIP bit in the status register will be set to a 1 and the erase operation will continue.

Further Resume commands are ignored.

Erase operations may be interrupted as often as necessary e.g. an erase suspend command could immediately follow an erase

resume command but, in order for an erase operation to progress to completion there must be some periods of time between

resume and the next suspend command greater than or equal to tERS. See Table 52 on page 120.

Figure 9.35 Erase Suspend Command Sequence

Erase Suspend Instruction

Read Status

Mode Command

Erase Suspend

tESL

CS#

SCK

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