STLC5465B datasheet(71/101 Pages) STMICROELECTRONICS

71 / 101 page

LP (i)

: LOOPBACK 0/7

LPi = 1, Output Multiplex i is put instead of Input Multiplex i (0

≤ i ≤ 7). LOOPBACKis transparent

or not in accordance with OMVi (bit of Output Multiplex Configuration Register).

LPi = 0, Normal case, Input Multiplex i(0

≤ i ≤ 7) is taken into account.

N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.

VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H

bit15

bit8

bit7

bit 0

OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0

After reset (0000)H

See definition in next Paragraph.

VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H

bit15

bit8

bit7

bit 0

OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0

After reset (0000)H

ST(i)0 : STEP0 for each Output Multiplex i(0

≤ i ≤ 7), delayed or not.

ST(i)1 : STEP1 for each Output Multiplex i(0

≤ i ≤ 7), delayed or not.

DEL(i); : DELAYED Multiplex i(0

≤ i ≤ 7).

DEL (i) ST (i) 1 ST (i) 0

STEP for each Output Multiplex 0/7 delayed or not

Each bit is transmitted on the rising edge of the double clock without delay.

Bit 0 is defined by Frame synchronization Signal.

Each bit is transmitted with 1/2 bit-time delay.

Each bit is transmitted with 1 bit-time delay.

Each bit is transmitted with 2 bit-time delay.

Each bit is transmitted with 1/2 bit-time advance.

Each bit is transmitted with 1 bit-time advance

Each bit is transmitted with 2 bit-time advance.

When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit.

1/2 bit time 244ns if TDM at 2048 kHz,

1/2 bit time 122ns if TDM at 4096 kHz.

OMV (i) : Output Multiplex Validated 0/7

OMVi =1, condition to have DOUTi pin active (0

≤ i ≤ 7).

OMVi =0, DOUTi pin is High Impedance continuously (0

≤ i ≤ 7).

N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.

VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H

bit15

bit8

bit7

bit 0

SW1

SW0

DR64 DR44 DR24 DR04 AISD

SGC

SAV

SGV

TS1

TS0

IMTD

After reset (0000)H

IMTD

: Increased Minimum Throughput Delay

When SI = 0 (bit of CMDR, variable delay mode) :

IMTD = 1, the minimum delay through the matrixmemory is three time slots whateverthe selected

TDM output.

IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the selected

TDM output.

When IMTD = 0, the input TDMs cannot be delayed versus the frame synchronization (Use

of IMCR is limited) and the output TDMs cannot be advanced versus the frame

synchronization.(Use of OMCR is limited).

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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