STLC5465B datasheet(76/101 Pages) STMICROELECTRONICS

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VIII - INTERNAL REGISTERS (continued)

TABLE: SWITCHING AT 16KB/S when ITS3 =1

ITS 3 ITS 2 ITS 1 ITS 0

Upstream

Source: D channels of one of 16

GCI channels

Destination: two bits of one TDM

Downstream

Source: two bits of one TDM

Destination: D channels of one of 16

GCI channels

The contents of D channels of GCI

0 /3 of multiplex DIN4 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 0 in bit 7/8

D channel of GCI 1 in bit 5/6

D channel of GCI 2 in bit 3/4

D channel of GCI 3 in bit 1/2

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 0/3 of multiplex

DOUT4

bit 7/8 in D channel of GCI 0

bit 5/6 in D channel of GCI 1

bit 3/4 in D channel of GCI 2

bit 1/2 in D channel of GCI 3

The contents of D channels of GCI

4/7 of multiplex DIN4 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 4 in bit 7/8

D channel of GCI 5 in bit 5/6

D channel of GCI 6 in bit 3/4

D channel of GCI 7 in bit 1/2

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 4/7 of multiplex

DOUT4.

bit 7/8 in D channel of GCI 4

bit 5/6 in D channel of GCI 5

bit 3/4 in D channel of GCI 6

bit 1/2 in D channel of GCI 7

The contents of D channels of GCI 0

/3 of multiplex DIN5 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 0 in bit 7/8

D channel of GCI 1 in bit 5/6

D channel of GCI 2 in bit 3/4

D channel of GCI 3 in bit 1/2

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 0/3 of multiplex

DOUT5.

bit 7/8 in D channel of GCI 0

bit 5/6 in D channel of GCI 1

bit 3/4 in D channel of GCI 2

bit 1/2 in D channel of GCI 3

The contents of D channels of GCI

4/7 of multiplex DIN5 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 4 in bit 7/8

D channel of GCI 5 in bit 5/6

D channel of GCI 6 in bit 3/4

D channel of GCI 7 in bit 1/2

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 4/7 of multiplex

DOUT5.

bit 7/8 in D channel of GCI 4

bit 5/6 in D channel of GCI 5

bit 3/4 in D channel of GCI 6

bit 1/2 in D channel of GCI 7

PRSA : Pseudo Random Sequence analyzer

If PRSA = 1, PRS analyzer is enabled during OTSy OTDMq and receives data :

INS = 0, data comes from Data Memory.

INS = 1 AND PRSG=1, Data comes from PRS Generator (Test Mode).

If PRSA = 0, PRS analyzer is disabled during OTSy OTDMq.

: Programmable Synchronization

If PS = 1, Programmable Synchronization Signal Pin is at ”1” during the bit time defined by OTSy

and OTDMq.

For OTSy and OTDMq with y = q = 0, PSS pin is at ”1” during the first bit of the frame defined

by the Frame synchronization Signal (FS).

If PS = 0, PSS Pin is at ”0” during the bit time defined by OTSy and OTDMq.

SCR

: Scrambler/ Descrambler

SCR=1, the scrambler or the descrambler are enabled. Both of them are located after the

switching matrix.

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