STLC5465B datasheet(39/101 Pages) STMICROELECTRONICS

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III - FUNCTIONAL DESCRIPTION (continued)

ADM0/16, NWE, NOE

ar e con necte dto each circuit

CE7

NCE5

NCE1

NCE3

NCE6

NCE4

NCE0

NCE2

DM8/15

DM0/7

128K x 16

128K x 8 circu it

Figure 25 :n x 128K x 16 SRAM Memory

Organization

RAS3

RAS2

RAS0

RAS1

DM8/15

DM0/7

256K x 16

CAS1

CAS0

ADM0/8, NWE , NO E a re conne cte d to ea ch circuit.

Figure 27 : 256K x 16 DRAM Circuit Organization

III.5.4 - SRAM interface

The SRAM space achieves 1 Mbyte max. It is

always organized in 16 bits. The structure of the

memory plane is shown in the following figures.

Because of the different chips usable, 19 address

wires and 8 NCE (Chip Enable) are necessary to

address the 1 Mbyte. The NCE selects the Most or

Least Significant Byte versus the value of A0 deliv-

ered by the

µP and the location of chip in the

memory space.

III.5.4.1 - 128K x 16 (up to 512K x 16) SRAM

This memory can be obtained with two 128K x 8

SRAM circuits (up to eight circuits)

Signals

A19

A18

A0 or equiv.

NCE7

NCE6

NCE5

NCE4

NCE3

NCE2

NCE1

NCE0

The Address bits delivered by the

Multi-HDLC for

128K x 8 SRAM circuits are :

ADM0/14 and ADM15/16 (17 bits) corresponding

with A1/17 delivered by the

µP.

The Address bits delivered by the

Multi-HDLC for

512K x n SRAM circuits are :

ADM0/14 and ADM15/18 (19 bits) corresponding

with A1/19 delivered by the

µP.

III.5.5 - DRAM Interface

In DRAM, the memory space can achieve up to 16

megabytes organized by 16 bits. Eleven address

wires, four NRAS and two NCAS are needed to

select any byte in the memory. One NRAS signal

selects 1 bank of 4 and the NCAS signals select the

bytes concerned by the transfer (1 or 2 selecting a

byte or a word). The DRAM memory interface is

then defined. The ”RAS only” refresh cycles will

refresh all memory locations. The refresh is pro-

grammable. The frequency of the refresh is fixed

by the memory requirements.

III.5.5.1 - 256K x n DRAM Signals

Signals

A20

A19

6800

NRAS3

NRAS2

NRAS1

NRAS0

NCAS1

UDS

NCAS0

LDS

The Address bits delivered by the

Multi-HDLC for

256K x n DRAM circuits are :

ADM0/8 (2 x 9 = 18 bits) corresponding with A1/18

delivered by the

µP.

III.5.4.2 - 512K x n SRAM

Signals

A0 or equiv.

NCE1

NCE0

ADM0/18, NWE, NOE

are conne cted to each circuit

NCE1

NCE0

DM8/15

DM0/7

512K x 16

512K x 8 circuit

Figure 26 :512K x 8 SRAM Circuit Memory

Organization

STLC5465B

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