STLC5465B datasheet(79/101 Pages) STMICROELECTRONICS

79 / 101 page

CACL : CYCLICAL ACCESS LIMITED

CACL = 1 (BID is ignored)

If Write Connection Memory, an automatic data write from Connection Memory Data Register

(CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS

0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location

is q +1 F(H).

If Read Connection Memory, an automatic transfer of data from Connection Memory into

Connection Memory Data Register (CMDR) after reading this last by the microprocessor

occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq

as defined by OM0/2. The last location is q +1 F(H).

CACL = 0, Write and Read Connection Memory in the normal way.

: Transparent Connection

TC = 1, (BID is ignored), if READ = 0 :

CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits

are ignored (Destination and Source are identical). The contents of Input time slot i - Input

multiplex j is switched into Output time slot i - Output multiplex j.

CAC = 0 and CACL = 1. Up to 32 ”Transparent Connections” are set up.

CAC = 1 and CACL = 0. Up to 256 ”Transparent Connections” are set up.

TC = 0, Write and Read Connection Memory are in accordance with BID.

VIII.10 - Sequence Fault Counter Register - SFCR (12)H

bit15

bit8

bit7

bit 0

F15

F14

F13

F12

F11

F10

F8F7F6

F5F4

F3F2F1

After reset (0000)H

When this register is read by the microprocessor, this register is reset (0000)H.

F0/15 : FAULT0/15

Number of faults detected by the Pseudo Random Sequence analyzer if the analyzer has been

validated and has recovered the receive sequence.

When the Fault Counter Register reaches (00FF)H it stays at its maximum value.

NB. As the SFCR is reset after reading, a 8-bit microprocessor must read the LSB that will represent the

number of faults between 0 and 255. To avoid overflow escape notice, it is necessary to start counting

at FF00h, by writing this value in SFCR before launching PRSA. If there are more than FFh errors, the

SFCO interrupt bit (see interrupt register IR -38H address) will signal that the fault count register has

reached the value FFFFh (because of the number of faults exceeded 255).

VIII.11 - Time Slot Assigner Address Register - TAAR (14)H

bit15

bit8

bit7

bit 0

TS4

TS3

TS2

TS1

TS0

READ

HDI

After reset (0100)H

READ : READ MEMORY

READ = 1, Read Time slot Assigner Memory.

READ = 0, Write Time slot Assigner Memory.

TS0/4 : TIME SLOTS0/4

These five bits define one of 32 time slots in which a channel is set-up or not.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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STLC5465B Datasheet(PDF) 79 Page - STMicroelectronics

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