STLC5465B datasheet(77/101 Pages) STMICROELECTRONICS

77 / 101 page

SCR

(cont’d)

: The scrambler is enabled when the output timeslot defined by the destination register (DSTR)

is an output timeslot belonging to any TDM except the two GCI multiplexes; the contents of this

output timeslot will be scrambled in accordance with the IUT-T V.29 Rec.

The descrambler is enabled when the output timeslot defined by the destinationregister (DSTR)

is an output timeslot belonging to the two GCI multiplexes except any TDM; the contents of this

output timeslot is descrambled in accordance with the IUT-T V.29 Rec.

Only 32 timeslots of 256 can be scrambled or/and descrambled:

GCI side, only B1 and B2 can be selected in each GCI channel (16 GCI channels are available:

8 per GCI multiplex).

*TDMside, it is forbiddento select a giventimeslot morethanoncewhenseveral TDMsare selected.

SCR=0,thescrambler orthedescrambleraredisabled;thecontentsofoutputtimeslotsarenotmodified.

VIII.9 - Connection Memory Address Register - CMAR (10)H

ACCESS MODE REGISTER (AMR)

DESTINATION REGISTER (DSTR)

bit15

bit8

bit7

bit 0

CACL

CAC

BID

READ OM2

OM1

OM0

OTS4 OTS3 OTS2 OTS1 OTS0

After reset (0800)H

This 16 bit register is constituted by two registers : DESTINATIONREGISTER (DSTR) and ACCESS MODE

DESTINATION REGISTER (DSTR)

When DSTR Register is written by the microprocessor, a memory access is launched. DSTR has two use

modes depending on CM (bit of CMAR).

CM = 1, access to connection memory (read or write) ;

OTS 0/4 : Output time slot 0/4 define OTSy with : 0

≤ y ≤ 31,

OM0/2

: Output Time Division Multiplex 0/2 define OTDMq with : 0

≤ q ≤ 7.

See table hereafter when DR04, DR24, DR44 and/or DR64 are at “1”; the bits of SMCR define the TDMs

at 4 Mbit/s.

The IM2/1 bits of Source Register (SRCR of CMDR) indicate the DIN pin number and the OM2/1 bits of

Destination Register (DSTR of CMAR) indicate the Dout pin number.

IM2 (bit7)

IM1 (bit6)

DIN pin

OM2 (bit7)

OM1(bit6)

DOUT pin

DIN0

DOUT0

DIN2

DOUT2

DIN4

DOUT4

DIN6

DOUT6

The ITS4/0 and IM0 bits of Source Register (SRCR of CMDR) indicate the input timeslot number. (IM0 bit

is the Least Significant Bit; it indicates either even timeslot or odd timeslot.

ITS4

(bit4)

ITS3

(bit3)

ITS2

(bit2)

ITS1

(bit1)

ITS0

(bit0)

IMO

(bit5)

Input timeslot number

0000

1111

VIII - INTERNAL REGISTERS (continued)

STLC5465B

77/101

STLC5465B Datasheet(PDF) 77 Page - STMicroelectronics

STLC5465B Datasheet(HTML) 77 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL