STLC5465B datasheet(25/101 Pages) STMICROELECTRONICS

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TIME S LOT ASS IGNER

32 Rx HDLC

32 ADDRES S

RECOGNITION

32 Rx FIFO’s

32 Rx DMAC

32 Tx FIFO’s

32 Tx HDLC

32 CSMA-CR

DIN 8

Dire ct HDLC Input

From Output 7

of the Matrix

To Input 7 of the Matrix

From Output 6

of the Matrix

DOUT 6

Direct HDLC Output

Conte ntion

Bus

Echo

µP

INTERFACE

RAM

INTERFACE

Figure 11 : HDLC and DMA Controller Block Diagram

III - FUNCTIONAL DESCRIPTION (continued)

III.2 - HDLC Controller

III.2.1 - Function Description

The internal HDLC controller can run up to 32

channels in a conventional HDLC mode or in a

transparent (non-HDLC) mode (configurable per

channel).

Each channel bit rate is programmablefrom 4kbit/s

to 64kbit/s. All the configurations are also possible

from 32 channels (from 4 to 64 kbit/s) to one

channel at 2 Mbit/s.

In reception, the HDLC time slots can directly come

from the input TDM DIN8 (direct HDLC Input) or

from any other TDM input after switching towards

the output 7 of the matrix (configurable per time

slot).

In transmission, the HDLC frames are sent on the

output DOUT6 and on the output CB (with or with-

out contention mechanism), or are switched to-

wards the other TDM output via the input 7 of the

matrix (see Figure 11).

III.2.1.1 - Format of the HDLC Frame

The format of an HDLC frame is the same in receive

and transmit direction and shown here after.

III.2.1.2 - Composition of an HDLC Frame

Opening Flag

Address Field (first byte)

Address Field (second byte)

Command Field (first byte)

Command Field (second byte)

Data (first byte)

Data (optional)

Data (last byte)

FCS (first byte)

FCS (second byte)

Closing Flag

- Opening Flag

- One or two bytes for address recognition (recep-

tion) and insertion (transmission)

- Data bytes with bit stuffing

- Frame Check Sequence: CRC with polynomial

G(x) = x

16 +x12+x5+1

- Closing Flag.

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