STLC5465B datasheet(2/101 Pages) STMICROELECTRONICS

2 / 101 page

TABLE OF CONTENTS

Page

I - PIN INFORMATION

... .. . . .... . . ... ....... . . ..... .. . . . . . . . . . 8

I.1 - Pin Connections . . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . .

I.2 - Pin Description . . . . . . . .... . . ... ....... . . ..... .. . . . . . . . . . 9

I.3 - Pin Definition . . . . . . . . . . . . .... ..... . . ..... ....... .. ... . . 13

I.3.1 - Input Pin Definition . . . . . . . . . . . . ...... ..... .... . . ... ...... 13

I.3.2 - Output Pin Definition . . . . . . . .... . . ....... .. . . ... ...... .... 13

I.3.3 - Input/OutputPin Definition . . . . . . . . . . ..... .. . . .... . . .. . . . . . . . 13

II - BLOCK DIAGRAM

... .. . . .... . . ... ....... . . ..... .. . . . . . . . . . 14

III - FUNCTIONAL DESCRIPTION ... .. . . .... . . ..... ..... . . ..... .. . . . 15

III.1 - The Switching Matrix N x 64 KBits/S . . . . . . .... ... ..... ..... . . .... 15

III.1.1 - Function Description

. . . . . . . . . . . . . . . . . . . . . . . ..... ........ 15

III.1.2 - Architecture of the Matrix . . . . . . . . . . ..... .. . . .... . . .. . . . . . . . 15

III.1.3 - Connection Function . . . . . . . . . . . . . . . . . . . . . . . ..... ........ 15

III.1.4 - Loop Back Function . . . . . . . .... . . ....... .. . . ... ...... .... 15

III.1.5 - Delay through the Matrix . . . . . . . . . . ..... .. . . .... . . .. . . . . . . . 17

III.1.5.1 - Variable Delay Mode . . . . . . . .... . . ..... ..... . . ..... .. . . . 17

III.1.5.2 - Sequence Integrity Mode . . . . . . . ....... .. .... . . . . . . . . ..... 17

III.1.6 - Connection Memory . . . . . . . .... . . ....... .. . . ... ...... .... 21

III.1.6.1 - Description . . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . . 21

III.1.6.2 - Access to Connection Memory . . . . . . . . . . . . . . . . . . . . . . . ..... . . 21

III.1.6.3 - Access to Data Memory . . . . . . . . . . ..... .. . . .... . . .. . . . . . . . 21

III.1.6.4 - Switching at 32 Kbit/s . . . . . . . .... . . ..... ..... . . ..... .. . . . 21

III.1.6.5 - Switching at 16 kbit/s . . . . . . . .... . . ..... ..... . . ..... .. . . . 21

III.2 - HDLC Controller . . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . . 25

III.2.1 - Function Description

. . . . . . . . . . . . . . . . . . . . . . . ..... ........ 25

III.2.1.1 - Format of the HDLC Frame . . . . . . . . . . . . . ..... ..... . . .. . . ... 25

III.2.1.2 - Composition of an HDLC Frame . . . . . . .... ... ..... ..... . . .... 25

III.2.1.3 - Description and Functions of the HDLC Bytes . . . . . . . . . . . . . ..... .... 26

III.2.2 - CSMA/CR Capability . . . . . . . . . . . . . . . . . . . . . . . ..... ........ 26

III.2.3 - Time Slot Assigner Memory . . . . . . . ....... .. .... . . . . . . . . ..... 27

III.2.4 - Data Storage Structure . . . . . . . .... . . ..... ..... . . ..... .. . . . 27

III.2.4.1 - Reception . . . . . . . .... . . ... ....... . . ..... .. . . . . . . . . . 27

III.2.4.2 - Transmission . . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..27

III.2.4.3 - Frame Relay

. . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..27

III.2.5 - Transparent Modes . . . . . . . .... . . ....... .. . . ... ...... .... 29

III.2.6 - Command of the HDLC Channels

. . . . . . .... ... ..... ..... . . .... 29

III.2.6.1 - Reception Control . . . . . . . .... . . ....... .. . . ... ...... .... 29

III.2.6.2 - Transmission Control . . . . . . . .... . . ..... ..... . . ..... .. . . . 29

III.3 - C/I and Monitor . . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . . 29

III.3.1 - Function Description

. . . . . . . . . . . . . . . . . . . . . . . ..... ........ 29

III.3.2 - GCI and V* Protocol . . . . . . . .... . . ....... .. . . ... ...... .... 30

III.3.3 - Structure of the Treatment . . . . . . . ....... .. .... . . . . . . . . ..... 30

STLC5465B

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