STLC5465B datasheet(88/101 Pages) STMICROELECTRONICS

88 / 101 page

NOBT : NUMBER OF BYTE which has been transmitted.

NOBT = 1, the first byte is transmitting.

NOB T = 0, the second byte is transmitting, the first byte has been transmitted.

: Last byte ; this L bit is the L bit which has been written by the microprocessor.

ABT

: ABORT

ABT=1, the remote receiver has aborted the current message.

: Time Out one millisecond

TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one

millisecond ago.

VIII.24 - Transmit Monitor Data Register - TMDR (2E)H

bit15

bit8

bit7

bit 0

M18

M17

M16

M15

M14

M13

M12

M11

M08

M07

M06

M05

M04

M03

M02

M01

After reset (FFFF)H

M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first.

M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first.

VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H

bit15

TDM5

bit8

bit7

TDM4

bit 0

MI71

MI61

MI51

MI41

MI31

MI21

MI11

MI01

MI70

MI60

MI50

MI40

MI30

MI20

MI10

MI00

After reset (0000)H

When the microprocessor read this register, this register is reset (0000)H.

MIxy

: Transmit Monitor Channel x Interrupt, Multiplex y with :

≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5

y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5.

MIxy = 1 when :

- a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In

this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or

- the message has been aborted by the remote receive Monitor Channel or

- the Timer has reached one millisecond (in accordancewith TIV bit of TMAR) by IM3 bit of IMR.

When MIxy goes to ”1”, the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked.

VIII.26 - Memory Interface Configuration Register - MICR (32)H

bit15

bit8

bit7

bit 0

P41

P40

P31

P30

P21

P20

P11

P10

REF

After reset (E4F0)H

REF

: MEMORY REFRESH

REF = 1, DRAM REFRESH is validated,

REF = 0, DRAM REFRESH is not validated.

R,S,T

: These three bits define the external RAM circuit organization (1word=2bytes)

The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 pin).

If refresh

128K x 8 SRAM circuit (up to 512K words)

512K x 8 SRAM circuit (up to 512K words)

256K x 16 DRAM circuit (up to 1M word)

512 cycles / 8ms

1M x 4 (or 16) bits DRAM circuit (up to 4M words)

1024 cycles / 16ms

4M x 4 (or 16) bits DRAM circuit (up to 8M words)

2048 cycles / 32ms

101 to 111 not used (this writting is forbidden)

The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 Pin).

VIII - INTERNAL REGISTERS (continued)

STLC5465B

88/101

STLC5465B Datasheet(PDF) 88 Page - STMicroelectronics

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