STLC5465B datasheet(82/101 Pages) STMICROELECTRONICS

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PEN

: CSMA PENALTY significant if CSMA = 1

PEN = 1, the penalty value is 1 ; a transmitter which has transmitted a frame correctly will count

(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8

or 10 given by the buffer descriptor related to the frame.

PEN = 0, the penalty value is 2 ; a transmitter which has transmitted a frame correctly will count

(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8

or 10 given by the transmit descriptor related to the frame).

: Common flag

CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next

frame is ready to be transmitted.

CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.

VIII.14 - HDLC Receive Command Register - HRCR (1A)H

bit15

bit8

bit7

bit 0

CH4

CH3

CH2

CH1

CH0

READ

AR21

AR20

AR11

AR10

CRC

After reset (0000)H

READ : READ COMMAND MEMORY

READ = 1, READ COMMAND MEMORY.

READ = 0, WRITE COMMAND MEMORY.

CH0/4 : These five bits define one of 32 channels.

C1/C0 : COMMAND

Commands Bits

ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the

reception, generates an interrupt and waits new command such as START orn CONTINUE.

If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits

a new command such as START or CONTINUE.

START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial

descriptor. The initial descriptor address is provided by the Initiate Block located in external

memory.

CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already received.

HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and

waits a new command such as START or CONTINUE.

P0/1

: PROTOCOL BITS

Transmission Mode

HDLC

Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.

Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.

Reserved

: Flag Monitoring.

This bit is a status bit read by the microprocessor.

FM=1: HDLC Controller is receiving a frame or HDLC Controller has just received one flag.

FM is put to 0 by the microprocessor.

CRC

: CRC stored in external memory

CRC = 1, the CRC is stored at the end of the frame in external memory.

CRC = 0, the CRC is not stored into external memory.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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