STLC5465B datasheet(81/101 Pages) STMICROELECTRONICS

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VIII.13 - HDLC Transmit Command Register - HTCR (18)H

bit15

bit8

bit7

bit 0

CH4

CH3

CH2

CH1

CH0

READ

PEN

CSMA

NCRC

After reset (0000)H

READ : READ COMMAND MEMORY

READ = 1, READ COMMAND MEMORY.

READ = 0, WRITE COMMAND MEMORY.

CH0/4 : These five bits define one of 32 channels.

C1/C0 : COMMAND BITS

Commands Bits

ABORT ; if this command occurs during the current frame, HDLC Controller transmits seven ”1”

immediately, afterwards HDLC Controller transmits ”1” or flag in accordance with F bit, generates

an interrupt and waits new command such as START orn CONTINUE.

If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and

waits a new command such as START or CONTINUE.

START ; Tx DMA Controller is now going to transfer first frame from buffer related to initial

descriptor. The initial descriptor address is provided by the Initiate Block located in external

memory.

CONTINUE ; Tx DMA Controller is now going to transfer next frame from buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already transmitted.

HALT ; after transmitting frame, HDLC Controller transmits ”1” or flag in accordance with F bit,

generates an interrupt and is waiting new command such as START or CONTINUE.

P0/1

: PROTOCOL BITS

Transmission Mode

HDLC

Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.

Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.

Reserved

: Flag

F = 1 ; flags are transmitted between closing flag of current frame and opening flag of next frame.

F = 0 ; ”1” are transmitted between closing flag of current frame and opening flag of next frame.

NCRC : CRC NOT TRANSMITTED

NCRC = 1, the CRC is not transmitted at the end of the frame.

NCR C =0, the CRC is transmitted at the end of the frame.

CSMA : Carrier Sense Multiple Access with Contention Resolution

CSMA = 1, CB output and the Echo Bit are taken into account during this channel transmission

by the Tx HDLC.

CSMA = 0, CB output and the Echo Bit are defined by V11 (see ” Time slot Assigner Data

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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