STLC5465B datasheet(74/101 Pages) STMICROELECTRONICS

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VIII.8 - Connection Memory Data Register - CMDR (0E)H

CONTROL REGISTER (CTLR)

SOURCE REGISTER (SRCR)

bit15

bit8

bit7

bit 0

SCR

PRSA

OTSV LOOP

IM2

IM1

IM0

ITS 4 ITS 3 ITS 2 ITS 1 ITS 0

After reset (0000)H

This 16 bit register is constituted by two registers :

SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR)

SOURCE REGISTER (SRCR) has two use modes depending on CM (bit of CMAR).

CM = 1, access to connection memory (read or write)

- PRSG = 0, ITS 0/4 and IM0/2 bits are defined hereafter :

ITS 0/4 : Input time slot 0/4 define ITSx with : 0

≤ x ≤ 31;

IM0/2

: Input Time Division Multiplex 0/2 define ITDMp with : 0

≤ p ≤ 7.

- PRSG = 1, the Pseudo Random Sequence Generator is validated, SRCR is not significant.

CM = 0, access to data memory (read only). SRC is the data register of the data memory.

CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multi-

plex OTDMq :

: SEQUENCE INTEGRITY

SI = 1, the delay is always : (31 - ITSx) + 32 + OTSy.

SI = 0, the delay is minimum to pass through the data memory.

LOOP : LOOPBACK per channel relevant if a bidirectional connection has been established.

LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq.

OTSV = 1, transparent Mode LOOPBACK.

OTSV = 0, not Transparent Mode LOOPBACK.

OTSV : OUTPUT TIME SLOT VALIDATED

OTSV = 1, OTSy OTDMq is enabled.

OTSV = 0, OTSy OTDMq is High Impedance.

(OTSy : Output Time slot with 0

≤ y ≤ 31;OTDMq : OutputTime Division Multiplex with 0 ≤ q ≤ 7).

VIII - INTERNAL REGISTERS (continued)

S1/S0 : SOURCE 1/0

Source for each timeslot of DOUT0/7

Data Memory (Normal case)

Connection Memory

D channels from/to GCI multiplexes (See note and table hereafter)

Pseudo Random Sequence Generator delivers Hyperchannel at n x 64Kb/s is possible.

Note:

Connection

When the source of D channels is selected (GCI channels defined by ITS 1/0) and when

the destination is selected (Output timeslot defined by OTS 0/4; output TDM defined by

OM 0/2) the upstream connection is set up; the downstream connection (reverse

direction TDM to GCI) is set up automatically if ITS 2 bit is at 1. So BID, bit of CMAR

must be written at”0”.

Release

Remember: write S1=1, S0=0 and ITS 2 bit = 0 to release the downstream connection;

the upstream connection is released when the source changes.

STLC5465B

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