STLC5465B datasheet(78/101 Pages) STMICROELECTRONICS

78 / 101 page

The OTS4/0 and OM0 bits of Destination Register (DSTR of CMAR) indicate the output timeslot number.

(OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot

OTS4

(bit4)

OTS3

(bit3)

OTS2

(bit2)

OTS1

(bit1)

OTS0

(bit0)

OMO

(bit5)

Output timeslot number

0000

1111

Nota Bene:

- CLOCK A/B is at 4 or at 8 MHz in accordance with HCL bit of General Configuration Register GCR (02).

HCL=1, bit clock frequency is at 8 192 KHz.

For a TDM at 4 Mbit/s or 2Mbit/s, each received bit is sampled at 3/4 bit-time.

HCL=0, bit clock frequency is at 4 096 KHz

For a TDM at 4 Mbit/s, each received bit is sampled at half bit-time.

For a TDM at 2 Mbit/s, each received bit is sampled at 3/4 bit-time.

The definition of IMCRO/1, OMCRO/1 are kept with bit time = 244 ns

Remarks:

- OM0, bit5 of DSTR indicates either even TDM or odd TDM if TDM at 2 Mb/s.

- OM0, bit5 of DSTR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s.

- IM0, bit5 of SRCR indicates either even TDM or odd TDM if TDM at 2 Mb/s.

- IM0, bit5 of SRCR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s.

- CAC = CACL = 0, DSTR is the Address Register of the Connection Memory;

- CAC or CACL = 1, DSTR is used to indicate the current address for the Connection Memory ; its contents

is assigned to the outputs.

CM = 0, access to data memory (read only) ;

- DSTR is the Address Register of the Data Memory; its contents is assigned to the inputs.

ACCESS MODE REGISTER (AMR)

READ : READ MEMORY

READ = 1, Read Connection Memory (or Data Memory in accordance with CM).

READ = 0, Write Connection Memory.

: CONNECTION MEMORY

CM = 1, Write or Read Connection Memory in accordance with READ.

CM = 0, Read only Data Memory (READ = 0 has no effect).

BID

: BIDIRECTIONAL CONNECTION

BID = 1; Two connections are set up:

ITSx ITDMp ------> OTSy OTDMq (LOOP of CMDR Register is taken into account) and

ITSy ITDMq ------> OTSx OTDMp (LOOP of CMDR Register is not taken into account).

BID = 0; One connection is set up:

ITSx ITDMp ------> OTSy OTDMq only.

CAC

: CYCLICAL ACCESS

CAC = 1 (BID is ignored)

if Write Connection Memory, an automatic data write from Connection Memory Data Register

(CMDR) up to 256 locations of Connection Memory occurs. The first address is indicated by the

if Read Connection Memory, an automatic transfer of data from the location indicated by the

microprocessor occurs. The last location is (FF)H.

CAC = 0, Write and Read Connection Memory in the normal way.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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STLC5465B Datasheet(PDF) 78 Page - STMicroelectronics

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