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UPD17708 Datasheet(PDF) 282 Page - NEC |
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UPD17708 Datasheet(HTML) 282 Page - NEC |
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282 / 356 page  282 µPD17704, 17705, 17707, 17708, 17709 Figure 18-8. Configuration of IF Counter Data Register Data buffer DBF3 DBF2 Name IF counter data register Symbol IFC Peripheral address 43H DBF1 DBF0 b3 b2 b1 b0 b6 b5 b4 b10 b9 b8 b7 b13 b12 b15 b14 b11 Peripheral register 0 Transfer data Valid data GET can be executed PUT changes nothing 16 Count value of frequency counter x 216–1 (FFFFH) IF counter function • FMIF count mode of FMIFC pin Counts rising edge of signal input to P1C0/FMIFC pin via 1/2 divider • AMIF count mode of AMIFC pin Counts rising edge of signal input to P1C1/AMIFC pin • AMIF count mode of FMIFC pin Counts rising edge of signal input to P1C0/FMIFC pin External gate counter function Counts rising edge of internal reference frequency signal from rising edge to next rising edge of signal input to P2A0/FCG0 or P2A1/FCG1 pin Once the IF counter data register has counted up to FFFFH, it remains at FFFFH until the counter is reset. |
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