UPD17708 datasheet(285/356 Pages) NEC

285 / 356 page

285

µPD17704, 17705, 17707, 17708, 17709

18.5 Using External Gate Counter

18.5.1 Program example of external gate counter

A program example of the external gate counter is shown below.

Example To use the P2A0/FCG0 pin as external gate input pin

INITFLG NOT IFCMD1, NOT IFCMD0, IFCCK1, NOT IFCCK0

; Selects external gate counter function and sets gate

time to 8 ms

INITFLG NOT FCGCH1, FCGCH0 ; Selects FCG0 pin as external gate input pin

SET1

IFCRES

; Resets counter

SET1

IFCSTRT

; Starts counting

LOOP:

SKF1

IFCGOSTT

; Detects opening or closing of gate

READ

; Branches to READ: if gate is closed

Processing A

; Do not read data of IF counter with this processing A

LOOP

READ:

GET

DBF, IFC

; Reads value of IF counter data register to data buffer

18.5.2 Error of external gate counter

The errors of the external gate counter include an internal frequency error and a count error. The following

paragraphs (1) and (2) describe each of these errors.

(1) Internal frequency error

The internal frequency of the external gate counter is created by dividing the 4.5-MHz clock. Therefore, if

the system clock is shifted from 4.5 MHz by “+x” ppm, the gate time is shifted by “–x” ppm.

(2) Count error

The external gate counter counts the frequency by the rising edge of the internal frequency.

If the internal frequency is low when the gate is opened (when the signal input to the pin rises), one excess

pulse is counted.

If the gate is closed (when the signal rises next time), the excess pulse is not counted due to the count level

of the internal frequency.

Therefore, the count error is “+1, –0”.

UPD17708 Datasheet(PDF) 285 Page - NEC

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