UPD17708 datasheet(287/356 Pages) NEC

287 / 356 page

287

µPD17704, 17705, 17707, 17708, 17709

19. BEEP

19.1 Outline of BEEP

Figure 19-1 outlines BEEP.

BEEP outputs a clock of 1, 3, 4, or 6.7 kHz from the P1D0/BEEP0 pin, and a clock of 4 kHz, 3 kHz, 200 Hz, or

67 Hz from the P1D1/BEEP1 pin.

The duty factor of the BEEP output is 50%.

Figure 19-1. Outline of BEEP

P1D0/BEEP0

P1D1/BEEP1

P1DBIO0 flag

BEEP0SEL flag

BEEP0CK1 falg

BEEP0CK0 falg

P1DBIO1 flag

BEEP1SEL flag

BEEP1CK1 flag

BEEP1CK0 flag

I/O selection

block

Output selection

flag

Clock

selection

block

I/O selection

block

Output selection

flag

Clock

selection

block

Output latch

Clock generation

block

1 kHz

3 kHz

4 kHz

6.7 kHz

67 Hz

200 Hz

Remarks 1.

BEEP0CK1 and BEEP0CK0 (bits 1 and 0 of BEEP clock selection register: refer to Figure 19-4)

select the output frequency of BEEP0.

BEEP1CK1 and BEEP1CK0 (bits 3 and 2 of BEEP clock selection register: refer to Figure 19-4)

select the output frequency of BEEP1.

BEEP1SEL and BEEP0SEL (bits 1 and 0 of BEEP/general-purpose port pin function selection

P1DBIO1 and P1DBIO0 (bits 1 and 0 of port 1D bit I/O selection register: refer to Figure 19-2) select

the input or output mode of the port.

UPD17708 Datasheet(PDF) 287 Page - NEC

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