UPD17708 datasheet(309/356 Pages) NEC

309 / 356 page

309

µPD17704, 17705, 17707, 17708, 17709

Figure 21-3. CE Reset Operation without Clock Stop Instruction (2/2)

(b) If status of CE pin changes while CE counter operates

At this time, the CE reset timer carry counter status is not affected.

21.2.2 CE reset with clock stop (STOP s) instruction used

Figure 21-4 shows the operation.

When the clock stop instruction is used, the clock stop signal is output when the “STOP s” instruction is executed,

and oscillation is stopped and the device operation is stopped.

When the CE pin goes high, the clock stop status is released, and oscillation is started (high level input of P0D

or INT pin interrupt can also be used as the clock stop status releasing conditions. For details, refer to 20. STANDBY).

If the basic timer 0 carry FF setting pulse goes high after the CE pin has gone high, the halt status is released,

and program execution is started from address 0 (CE reset).

As the set time (tSET) of the basic timer 0 carry FF setting pulse, the value immediately before the clock stop

instruction is executed is retained.

Because the set value of the CE reset timer carry counter is initialized to 1, CE reset is effected tSET/2 after the

CE pin has gone high.

VDD

XOUT

BTM0CY flag

setting pulse

CE reset timer

carry counter

Set value of CE reset

timer carry counter

CE reset signal

5 V

0 V

tSET

N–2

N–1

CE reset

UPD17708 Datasheet(PDF) 309 Page - NEC